1*f07c776fSEnric Balletbo i Serra /* SPDX-License-Identifier: GPL-2.0 */ 2*f07c776fSEnric Balletbo i Serra /* 3*f07c776fSEnric Balletbo i Serra * Copyright (c) 2019 MediaTek Inc. 4*f07c776fSEnric Balletbo i Serra * Author: Yong Liang <yong.liang@mediatek.com> 5*f07c776fSEnric Balletbo i Serra */ 6*f07c776fSEnric Balletbo i Serra 7*f07c776fSEnric Balletbo i Serra #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 8*f07c776fSEnric Balletbo i Serra #define _DT_BINDINGS_RESET_CONTROLLER_MT2712 9*f07c776fSEnric Balletbo i Serra 10*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_INFRA_SW_RST 0 11*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_MM_SW_RST 1 12*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_MFG_SW_RST 2 13*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_VENC_SW_RST 3 14*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_VDEC_SW_RST 4 15*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_IMG_SW_RST 5 16*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_INFRA_AO_SW_RST 8 17*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_USB_SW_RST 9 18*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_APMIXED_SW_RST 10 19*f07c776fSEnric Balletbo i Serra 20*f07c776fSEnric Balletbo i Serra #define MT2712_TOPRGU_SW_RST_NUM 11 21*f07c776fSEnric Balletbo i Serra 22*f07c776fSEnric Balletbo i Serra #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ 23