1c4e181d6SAnson Huang /* SPDX-License-Identifier: GPL-2.0-only */ 2c4e181d6SAnson Huang /* 3c4e181d6SAnson Huang * Copyright 2020 NXP 4c4e181d6SAnson Huang */ 5c4e181d6SAnson Huang 6c4e181d6SAnson Huang #ifndef DT_BINDING_RESET_IMX8MP_H 7c4e181d6SAnson Huang #define DT_BINDING_RESET_IMX8MP_H 8c4e181d6SAnson Huang 9c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_POR_RESET0 0 10c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_POR_RESET1 1 11c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_POR_RESET2 2 12c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_POR_RESET3 3 13c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_RESET0 4 14c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_RESET1 5 15c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_RESET2 6 16c4e181d6SAnson Huang #define IMX8MP_RESET_A53_CORE_RESET3 7 17c4e181d6SAnson Huang #define IMX8MP_RESET_A53_DBG_RESET0 8 18c4e181d6SAnson Huang #define IMX8MP_RESET_A53_DBG_RESET1 9 19c4e181d6SAnson Huang #define IMX8MP_RESET_A53_DBG_RESET2 10 20c4e181d6SAnson Huang #define IMX8MP_RESET_A53_DBG_RESET3 11 21c4e181d6SAnson Huang #define IMX8MP_RESET_A53_ETM_RESET0 12 22c4e181d6SAnson Huang #define IMX8MP_RESET_A53_ETM_RESET1 13 23c4e181d6SAnson Huang #define IMX8MP_RESET_A53_ETM_RESET2 14 24c4e181d6SAnson Huang #define IMX8MP_RESET_A53_ETM_RESET3 15 25c4e181d6SAnson Huang #define IMX8MP_RESET_A53_SOC_DBG_RESET 16 26c4e181d6SAnson Huang #define IMX8MP_RESET_A53_L2RESET 17 27c4e181d6SAnson Huang #define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 28c4e181d6SAnson Huang #define IMX8MP_RESET_OTG1_PHY_RESET 19 29c4e181d6SAnson Huang #define IMX8MP_RESET_OTG2_PHY_RESET 20 30c4e181d6SAnson Huang #define IMX8MP_RESET_SUPERMIX_RESET 21 31c4e181d6SAnson Huang #define IMX8MP_RESET_AUDIOMIX_RESET 22 32c4e181d6SAnson Huang #define IMX8MP_RESET_MLMIX_RESET 23 33c4e181d6SAnson Huang #define IMX8MP_RESET_PCIEPHY 24 34c4e181d6SAnson Huang #define IMX8MP_RESET_PCIEPHY_PERST 25 35c4e181d6SAnson Huang #define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 36c4e181d6SAnson Huang #define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 37c4e181d6SAnson Huang #define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 38c4e181d6SAnson Huang #define IMX8MP_RESET_MEDIA_RESET 29 39c4e181d6SAnson Huang #define IMX8MP_RESET_GPU2D_RESET 30 40c4e181d6SAnson Huang #define IMX8MP_RESET_GPU3D_RESET 31 41c4e181d6SAnson Huang #define IMX8MP_RESET_GPU_RESET 32 42c4e181d6SAnson Huang #define IMX8MP_RESET_VPU_RESET 33 43c4e181d6SAnson Huang #define IMX8MP_RESET_VPU_G1_RESET 34 44c4e181d6SAnson Huang #define IMX8MP_RESET_VPU_G2_RESET 35 45c4e181d6SAnson Huang #define IMX8MP_RESET_VPUVC8KE_RESET 36 46c4e181d6SAnson Huang #define IMX8MP_RESET_NOC_RESET 37 47c4e181d6SAnson Huang 48c4e181d6SAnson Huang #define IMX8MP_RESET_NUM 38 49c4e181d6SAnson Huang 50c4e181d6SAnson Huang #endif 51