1abf97755SAndrey Smirnov /* 2abf97755SAndrey Smirnov * Copyright (C) 2017 Impinj, Inc. 3abf97755SAndrey Smirnov * 4abf97755SAndrey Smirnov * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 5abf97755SAndrey Smirnov * 6abf97755SAndrey Smirnov * This program is free software; you can redistribute it and/or modify it 7abf97755SAndrey Smirnov * under the terms and conditions of the GNU General Public License, 8abf97755SAndrey Smirnov * version 2, as published by the Free Software Foundation. 9abf97755SAndrey Smirnov * 10abf97755SAndrey Smirnov * This program is distributed in the hope it will be useful, but WITHOUT 11abf97755SAndrey Smirnov * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12abf97755SAndrey Smirnov * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13abf97755SAndrey Smirnov * more details. 14abf97755SAndrey Smirnov * 15abf97755SAndrey Smirnov * You should have received a copy of the GNU General Public License 16abf97755SAndrey Smirnov * along with this program. If not, see <http://www.gnu.org/licenses/>. 17abf97755SAndrey Smirnov */ 18abf97755SAndrey Smirnov 19abf97755SAndrey Smirnov #ifndef DT_BINDING_RESET_IMX7_H 20abf97755SAndrey Smirnov #define DT_BINDING_RESET_IMX7_H 21abf97755SAndrey Smirnov 22abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_POR_RESET0 0 23abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_POR_RESET1 1 24abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_RESET0 2 25abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_RESET1 3 26abf97755SAndrey Smirnov #define IMX7_RESET_A7_DBG_RESET0 4 27abf97755SAndrey Smirnov #define IMX7_RESET_A7_DBG_RESET1 5 28abf97755SAndrey Smirnov #define IMX7_RESET_A7_ETM_RESET0 6 29abf97755SAndrey Smirnov #define IMX7_RESET_A7_ETM_RESET1 7 30abf97755SAndrey Smirnov #define IMX7_RESET_A7_SOC_DBG_RESET 8 31abf97755SAndrey Smirnov #define IMX7_RESET_A7_L2RESET 9 32abf97755SAndrey Smirnov #define IMX7_RESET_SW_M4C_RST 10 33abf97755SAndrey Smirnov #define IMX7_RESET_SW_M4P_RST 11 34abf97755SAndrey Smirnov #define IMX7_RESET_EIM_RST 12 35abf97755SAndrey Smirnov #define IMX7_RESET_HSICPHY_PORT_RST 13 36abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY1_POR 14 37abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY1_PORT_RST 15 38abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY2_POR 16 39abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY2_PORT_RST 17 40abf97755SAndrey Smirnov #define IMX7_RESET_MIPI_PHY_MRST 18 41abf97755SAndrey Smirnov #define IMX7_RESET_MIPI_PHY_SRST 19 42abf97755SAndrey Smirnov 43abf97755SAndrey Smirnov /* 44abf97755SAndrey Smirnov * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN 45abf97755SAndrey Smirnov * and PCIEPHY_G_RST 46abf97755SAndrey Smirnov */ 47abf97755SAndrey Smirnov #define IMX7_RESET_PCIEPHY 20 48abf97755SAndrey Smirnov #define IMX7_RESET_PCIEPHY_PERST 21 49abf97755SAndrey Smirnov 50abf97755SAndrey Smirnov /* 51abf97755SAndrey Smirnov * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it 52abf97755SAndrey Smirnov * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht 53abf97755SAndrey Smirnov * of as one 54abf97755SAndrey Smirnov */ 55abf97755SAndrey Smirnov #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 56abf97755SAndrey Smirnov #define IMX7_RESET_DDRC_PRST 23 57abf97755SAndrey Smirnov #define IMX7_RESET_DDRC_CORE_RST 24 58abf97755SAndrey Smirnov 59abf97755SAndrey Smirnov #define IMX7_RESET_NUM 25 60abf97755SAndrey Smirnov 61abf97755SAndrey Smirnov #endif 62abf97755SAndrey Smirnov 63