19952f691SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2abf97755SAndrey Smirnov /* 3abf97755SAndrey Smirnov * Copyright (C) 2017 Impinj, Inc. 4abf97755SAndrey Smirnov * 5abf97755SAndrey Smirnov * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 6abf97755SAndrey Smirnov */ 7abf97755SAndrey Smirnov 8abf97755SAndrey Smirnov #ifndef DT_BINDING_RESET_IMX7_H 9abf97755SAndrey Smirnov #define DT_BINDING_RESET_IMX7_H 10abf97755SAndrey Smirnov 11abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_POR_RESET0 0 12abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_POR_RESET1 1 13abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_RESET0 2 14abf97755SAndrey Smirnov #define IMX7_RESET_A7_CORE_RESET1 3 15abf97755SAndrey Smirnov #define IMX7_RESET_A7_DBG_RESET0 4 16abf97755SAndrey Smirnov #define IMX7_RESET_A7_DBG_RESET1 5 17abf97755SAndrey Smirnov #define IMX7_RESET_A7_ETM_RESET0 6 18abf97755SAndrey Smirnov #define IMX7_RESET_A7_ETM_RESET1 7 19abf97755SAndrey Smirnov #define IMX7_RESET_A7_SOC_DBG_RESET 8 20abf97755SAndrey Smirnov #define IMX7_RESET_A7_L2RESET 9 21abf97755SAndrey Smirnov #define IMX7_RESET_SW_M4C_RST 10 22abf97755SAndrey Smirnov #define IMX7_RESET_SW_M4P_RST 11 23abf97755SAndrey Smirnov #define IMX7_RESET_EIM_RST 12 24abf97755SAndrey Smirnov #define IMX7_RESET_HSICPHY_PORT_RST 13 25abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY1_POR 14 26abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY1_PORT_RST 15 27abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY2_POR 16 28abf97755SAndrey Smirnov #define IMX7_RESET_USBPHY2_PORT_RST 17 29abf97755SAndrey Smirnov #define IMX7_RESET_MIPI_PHY_MRST 18 30abf97755SAndrey Smirnov #define IMX7_RESET_MIPI_PHY_SRST 19 31abf97755SAndrey Smirnov 32abf97755SAndrey Smirnov /* 33abf97755SAndrey Smirnov * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN 34abf97755SAndrey Smirnov * and PCIEPHY_G_RST 35abf97755SAndrey Smirnov */ 36abf97755SAndrey Smirnov #define IMX7_RESET_PCIEPHY 20 37abf97755SAndrey Smirnov #define IMX7_RESET_PCIEPHY_PERST 21 38abf97755SAndrey Smirnov 39abf97755SAndrey Smirnov /* 40abf97755SAndrey Smirnov * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it 41abf97755SAndrey Smirnov * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht 42abf97755SAndrey Smirnov * of as one 43abf97755SAndrey Smirnov */ 44abf97755SAndrey Smirnov #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 45abf97755SAndrey Smirnov #define IMX7_RESET_DDRC_PRST 23 46abf97755SAndrey Smirnov #define IMX7_RESET_DDRC_CORE_RST 24 47abf97755SAndrey Smirnov 48de248327SLeonard Crestez #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 49de248327SLeonard Crestez 50de248327SLeonard Crestez #define IMX7_RESET_NUM 26 51abf97755SAndrey Smirnov 52abf97755SAndrey Smirnov #endif 53abf97755SAndrey Smirnov 54