1 /* SPDX-License-Identifier: GPL-2.0 */
2 /**
3  * This header provides index for the reset controller
4  * based on hi6220 SoC.
5  */
6 #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
7 #define _DT_BINDINGS_RESET_CONTROLLER_HI6220
8 
9 #define PERIPH_RSTDIS0_MMC0             0x000
10 #define PERIPH_RSTDIS0_MMC1             0x001
11 #define PERIPH_RSTDIS0_MMC2             0x002
12 #define PERIPH_RSTDIS0_NANDC            0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS       0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY      0x005
15 #define PERIPH_RSTDIS0_USBOTG           0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K       0x007
17 #define PERIPH_RSTDIS1_HIFI             0x100
18 #define PERIPH_RSTDIS1_DIGACODEC        0x105
19 #define PERIPH_RSTEN2_IPF               0x200
20 #define PERIPH_RSTEN2_SOCP              0x201
21 #define PERIPH_RSTEN2_DMAC              0x202
22 #define PERIPH_RSTEN2_SECENG            0x203
23 #define PERIPH_RSTEN2_ABB               0x204
24 #define PERIPH_RSTEN2_HPM0              0x205
25 #define PERIPH_RSTEN2_HPM1              0x206
26 #define PERIPH_RSTEN2_HPM2              0x207
27 #define PERIPH_RSTEN2_HPM3              0x208
28 #define PERIPH_RSTEN3_CSSYS             0x300
29 #define PERIPH_RSTEN3_I2C0              0x301
30 #define PERIPH_RSTEN3_I2C1              0x302
31 #define PERIPH_RSTEN3_I2C2              0x303
32 #define PERIPH_RSTEN3_I2C3              0x304
33 #define PERIPH_RSTEN3_UART1             0x305
34 #define PERIPH_RSTEN3_UART2             0x306
35 #define PERIPH_RSTEN3_UART3             0x307
36 #define PERIPH_RSTEN3_UART4             0x308
37 #define PERIPH_RSTEN3_SSP               0x309
38 #define PERIPH_RSTEN3_PWM               0x30a
39 #define PERIPH_RSTEN3_BLPWM             0x30b
40 #define PERIPH_RSTEN3_TSENSOR           0x30c
41 #define PERIPH_RSTEN3_DAPB              0x312
42 #define PERIPH_RSTEN3_HKADC             0x313
43 #define PERIPH_RSTEN3_CODEC_SSI         0x314
44 #define PERIPH_RSTEN3_PMUSSI1           0x316
45 #define PERIPH_RSTEN8_RS0               0x400
46 #define PERIPH_RSTEN8_RS2               0x401
47 #define PERIPH_RSTEN8_RS3               0x402
48 #define PERIPH_RSTEN8_MS0               0x403
49 #define PERIPH_RSTEN8_MS2               0x405
50 #define PERIPH_RSTEN8_XG2RAM0           0x406
51 #define PERIPH_RSTEN8_X2SRAM_TZMA       0x407
52 #define PERIPH_RSTEN8_SRAM              0x408
53 #define PERIPH_RSTEN8_HARQ              0x40a
54 #define PERIPH_RSTEN8_DDRC              0x40c
55 #define PERIPH_RSTEN8_DDRC_APB          0x40d
56 #define PERIPH_RSTEN8_DDRPACK_APB       0x40e
57 #define PERIPH_RSTEN8_DDRT              0x411
58 #define PERIPH_RSDIST9_CARM_DAP         0x500
59 #define PERIPH_RSDIST9_CARM_ATB         0x501
60 #define PERIPH_RSDIST9_CARM_LBUS        0x502
61 #define PERIPH_RSDIST9_CARM_POR         0x503
62 #define PERIPH_RSDIST9_CARM_CORE        0x504
63 #define PERIPH_RSDIST9_CARM_DBG         0x505
64 #define PERIPH_RSDIST9_CARM_L2          0x506
65 #define PERIPH_RSDIST9_CARM_SOCDBG      0x507
66 #define PERIPH_RSDIST9_CARM_ETM         0x508
67 
68 #define MEDIA_G3D                       0
69 #define MEDIA_CODEC_VPU                 2
70 #define MEDIA_CODEC_JPEG                3
71 #define MEDIA_ISP                       4
72 #define MEDIA_ADE                       5
73 #define MEDIA_MMU                       6
74 #define MEDIA_XG2RAM1                   7
75 
76 #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
77