111ea09b9SSerge Semin /* SPDX-License-Identifier: GPL-2.0-only */ 211ea09b9SSerge Semin /* 311ea09b9SSerge Semin * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 411ea09b9SSerge Semin * 511ea09b9SSerge Semin * Baikal-T1 CCU reset indices 611ea09b9SSerge Semin */ 711ea09b9SSerge Semin #ifndef __DT_BINDINGS_RESET_BT1_CCU_H 811ea09b9SSerge Semin #define __DT_BINDINGS_RESET_BT1_CCU_H 911ea09b9SSerge Semin 1011ea09b9SSerge Semin #define CCU_AXI_MAIN_RST 0 1111ea09b9SSerge Semin #define CCU_AXI_DDR_RST 1 1211ea09b9SSerge Semin #define CCU_AXI_SATA_RST 2 1311ea09b9SSerge Semin #define CCU_AXI_GMAC0_RST 3 1411ea09b9SSerge Semin #define CCU_AXI_GMAC1_RST 4 1511ea09b9SSerge Semin #define CCU_AXI_XGMAC_RST 5 1611ea09b9SSerge Semin #define CCU_AXI_PCIE_M_RST 6 1711ea09b9SSerge Semin #define CCU_AXI_PCIE_S_RST 7 1811ea09b9SSerge Semin #define CCU_AXI_USB_RST 8 1911ea09b9SSerge Semin #define CCU_AXI_HWA_RST 9 2011ea09b9SSerge Semin #define CCU_AXI_SRAM_RST 10 2111ea09b9SSerge Semin 2211ea09b9SSerge Semin #define CCU_SYS_SATA_REF_RST 0 2311ea09b9SSerge Semin #define CCU_SYS_APB_RST 1 24*c0cd3b17SSerge Semin #define CCU_SYS_DDR_FULL_RST 2 25*c0cd3b17SSerge Semin #define CCU_SYS_DDR_INIT_RST 3 26*c0cd3b17SSerge Semin #define CCU_SYS_PCIE_PCS_PHY_RST 4 27*c0cd3b17SSerge Semin #define CCU_SYS_PCIE_PIPE0_RST 5 28*c0cd3b17SSerge Semin #define CCU_SYS_PCIE_CORE_RST 6 29*c0cd3b17SSerge Semin #define CCU_SYS_PCIE_PWR_RST 7 30*c0cd3b17SSerge Semin #define CCU_SYS_PCIE_STICKY_RST 8 31*c0cd3b17SSerge Semin #define CCU_SYS_PCIE_NSTICKY_RST 9 32*c0cd3b17SSerge Semin #define CCU_SYS_PCIE_HOT_RST 10 3311ea09b9SSerge Semin 3411ea09b9SSerge Semin #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ 35