15d9730b9SXingyu Chen /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 25d9730b9SXingyu Chen * 35d9730b9SXingyu Chen * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 45d9730b9SXingyu Chen * Author: Xingyu Chen <xingyu.chen@amlogic.com> 55d9730b9SXingyu Chen * 65d9730b9SXingyu Chen */ 75d9730b9SXingyu Chen 85d9730b9SXingyu Chen #ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 95d9730b9SXingyu Chen #define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 105d9730b9SXingyu Chen 115d9730b9SXingyu Chen /* RESET0 */ 125d9730b9SXingyu Chen /* 0 */ 135d9730b9SXingyu Chen #define RESET_AM2AXI_VAD 1 145d9730b9SXingyu Chen /* 2-3 */ 155d9730b9SXingyu Chen #define RESET_PSRAM 4 165d9730b9SXingyu Chen #define RESET_PAD_CTRL 5 175d9730b9SXingyu Chen /* 6 */ 185d9730b9SXingyu Chen #define RESET_TEMP_SENSOR 7 195d9730b9SXingyu Chen #define RESET_AM2AXI_DEV 8 205d9730b9SXingyu Chen /* 9 */ 215d9730b9SXingyu Chen #define RESET_SPICC_A 10 225d9730b9SXingyu Chen #define RESET_MSR_CLK 11 235d9730b9SXingyu Chen #define RESET_AUDIO 12 245d9730b9SXingyu Chen #define RESET_ANALOG_CTRL 13 255d9730b9SXingyu Chen #define RESET_SAR_ADC 14 265d9730b9SXingyu Chen #define RESET_AUDIO_VAD 15 275d9730b9SXingyu Chen #define RESET_CEC 16 285d9730b9SXingyu Chen #define RESET_PWM_EF 17 295d9730b9SXingyu Chen #define RESET_PWM_CD 18 305d9730b9SXingyu Chen #define RESET_PWM_AB 19 315d9730b9SXingyu Chen /* 20 */ 325d9730b9SXingyu Chen #define RESET_IR_CTRL 21 335d9730b9SXingyu Chen #define RESET_I2C_S_A 22 345d9730b9SXingyu Chen /* 23 */ 355d9730b9SXingyu Chen #define RESET_I2C_M_D 24 365d9730b9SXingyu Chen #define RESET_I2C_M_C 25 375d9730b9SXingyu Chen #define RESET_I2C_M_B 26 385d9730b9SXingyu Chen #define RESET_I2C_M_A 27 395d9730b9SXingyu Chen #define RESET_I2C_PROD_AHB 28 405d9730b9SXingyu Chen #define RESET_I2C_PROD 29 415d9730b9SXingyu Chen /* 30-31 */ 425d9730b9SXingyu Chen 435d9730b9SXingyu Chen /* RESET1 */ 445d9730b9SXingyu Chen #define RESET_ACODEC 32 455d9730b9SXingyu Chen #define RESET_DMA 33 465d9730b9SXingyu Chen #define RESET_SD_EMMC_A 34 475d9730b9SXingyu Chen /* 35 */ 485d9730b9SXingyu Chen #define RESET_USBCTRL 36 495d9730b9SXingyu Chen /* 37 */ 505d9730b9SXingyu Chen #define RESET_USBPHY 38 515d9730b9SXingyu Chen /* 39-41 */ 525d9730b9SXingyu Chen #define RESET_RSA 42 535d9730b9SXingyu Chen #define RESET_DMC 43 545d9730b9SXingyu Chen /* 44 */ 555d9730b9SXingyu Chen #define RESET_IRQ_CTRL 45 565d9730b9SXingyu Chen /* 46 */ 575d9730b9SXingyu Chen #define RESET_NIC_VAD 47 585d9730b9SXingyu Chen #define RESET_NIC_AXI 48 595d9730b9SXingyu Chen #define RESET_RAMA 49 605d9730b9SXingyu Chen #define RESET_RAMB 50 615d9730b9SXingyu Chen /* 51-52 */ 625d9730b9SXingyu Chen #define RESET_ROM 53 635d9730b9SXingyu Chen #define RESET_SPIFC 54 645d9730b9SXingyu Chen #define RESET_GIC 55 655d9730b9SXingyu Chen #define RESET_UART_C 56 665d9730b9SXingyu Chen #define RESET_UART_B 57 675d9730b9SXingyu Chen #define RESET_UART_A 58 685d9730b9SXingyu Chen #define RESET_OSC_RING 59 695d9730b9SXingyu Chen /* 60-63 */ 705d9730b9SXingyu Chen 715d9730b9SXingyu Chen /* RESET2 */ 725d9730b9SXingyu Chen /* 64-95 */ 735d9730b9SXingyu Chen 745d9730b9SXingyu Chen #endif 75