1 /* 2 * Copyright (C) 2016 Intel Corporation. All rights reserved 3 * Copyright (C) 2016 Altera Corporation. All rights reserved 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" 18 */ 19 20 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 21 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 22 23 /* MPUMODRST */ 24 #define CPU0_RESET 0 25 #define CPU1_RESET 1 26 #define CPU2_RESET 2 27 #define CPU3_RESET 3 28 29 /* PER0MODRST */ 30 #define EMAC0_RESET 32 31 #define EMAC1_RESET 33 32 #define EMAC2_RESET 34 33 #define USB0_RESET 35 34 #define USB1_RESET 36 35 #define NAND_RESET 37 36 /* 38 is empty */ 37 #define SDMMC_RESET 39 38 #define EMAC0_OCP_RESET 40 39 #define EMAC1_OCP_RESET 41 40 #define EMAC2_OCP_RESET 42 41 #define USB0_OCP_RESET 43 42 #define USB1_OCP_RESET 44 43 #define NAND_OCP_RESET 45 44 /* 46 is empty */ 45 #define SDMMC_OCP_RESET 47 46 #define DMA_RESET 48 47 #define SPIM0_RESET 49 48 #define SPIM1_RESET 50 49 #define SPIS0_RESET 51 50 #define SPIS1_RESET 52 51 #define DMA_OCP_RESET 53 52 #define EMAC_PTP_RESET 54 53 /* 55 is empty*/ 54 #define DMAIF0_RESET 56 55 #define DMAIF1_RESET 57 56 #define DMAIF2_RESET 58 57 #define DMAIF3_RESET 59 58 #define DMAIF4_RESET 60 59 #define DMAIF5_RESET 61 60 #define DMAIF6_RESET 62 61 #define DMAIF7_RESET 63 62 63 /* PER1MODRST */ 64 #define WATCHDOG0_RESET 64 65 #define WATCHDOG1_RESET 65 66 #define WATCHDOG2_RESET 66 67 #define WATCHDOG3_RESET 67 68 #define L4SYSTIMER0_RESET 68 69 #define L4SYSTIMER1_RESET 69 70 #define SPTIMER0_RESET 70 71 #define SPTIMER1_RESET 71 72 #define I2C0_RESET 72 73 #define I2C1_RESET 73 74 #define I2C2_RESET 74 75 #define I2C3_RESET 75 76 #define I2C4_RESET 76 77 /* 77-79 is empty */ 78 #define UART0_RESET 80 79 #define UART1_RESET 81 80 /* 82-87 is empty */ 81 #define GPIO0_RESET 88 82 #define GPIO1_RESET 89 83 84 /* BRGMODRST */ 85 #define SOC2FPGA_RESET 96 86 #define LWHPS2FPGA_RESET 97 87 #define FPGA2SOC_RESET 98 88 #define F2SSDRAM0_RESET 99 89 #define F2SSDRAM1_RESET 100 90 #define F2SSDRAM2_RESET 101 91 #define DDRSCH_RESET 102 92 93 /* COLDMODRST */ 94 #define CPUPO0_RESET 160 95 #define CPUPO1_RESET 161 96 #define CPUPO2_RESET 162 97 #define CPUPO3_RESET 163 98 /* 164-167 is empty */ 99 #define L2_RESET 168 100 101 /* DBGMODRST */ 102 #define DBG_RESET 224 103 #define CSDAP_RESET 225 104 105 /* TAPMODRST */ 106 #define TAP_RESET 256 107 108 #endif 109