1fac1d443SCristian Ciocaltea /* SPDX-License-Identifier: GPL-2.0+ */ 2fac1d443SCristian Ciocaltea /* 3fac1d443SCristian Ciocaltea * Device Tree binding constants for Actions Semi S500 Reset Management Unit 4fac1d443SCristian Ciocaltea * 5fac1d443SCristian Ciocaltea * Copyright (c) 2014 Actions Semi Inc. 6fac1d443SCristian Ciocaltea * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> 7fac1d443SCristian Ciocaltea */ 8fac1d443SCristian Ciocaltea 9fac1d443SCristian Ciocaltea #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H 10fac1d443SCristian Ciocaltea #define __DT_BINDINGS_ACTIONS_S500_RESET_H 11fac1d443SCristian Ciocaltea 12fac1d443SCristian Ciocaltea #define RESET_DMAC 0 13fac1d443SCristian Ciocaltea #define RESET_NORIF 1 14fac1d443SCristian Ciocaltea #define RESET_DDR 2 15fac1d443SCristian Ciocaltea #define RESET_NANDC 3 16fac1d443SCristian Ciocaltea #define RESET_SD0 4 17fac1d443SCristian Ciocaltea #define RESET_SD1 5 18fac1d443SCristian Ciocaltea #define RESET_PCM1 6 19fac1d443SCristian Ciocaltea #define RESET_DE 7 20fac1d443SCristian Ciocaltea #define RESET_LCD 8 21fac1d443SCristian Ciocaltea #define RESET_SD2 9 22fac1d443SCristian Ciocaltea #define RESET_DSI 10 23fac1d443SCristian Ciocaltea #define RESET_CSI 11 24fac1d443SCristian Ciocaltea #define RESET_BISP 12 25fac1d443SCristian Ciocaltea #define RESET_KEY 13 26fac1d443SCristian Ciocaltea #define RESET_GPIO 14 27fac1d443SCristian Ciocaltea #define RESET_AUDIO 15 28fac1d443SCristian Ciocaltea #define RESET_PCM0 16 29fac1d443SCristian Ciocaltea #define RESET_VDE 17 30fac1d443SCristian Ciocaltea #define RESET_VCE 18 31fac1d443SCristian Ciocaltea #define RESET_GPU3D 19 32fac1d443SCristian Ciocaltea #define RESET_NIC301 20 33fac1d443SCristian Ciocaltea #define RESET_LENS 21 34fac1d443SCristian Ciocaltea #define RESET_PERIPHRESET 22 35fac1d443SCristian Ciocaltea #define RESET_USB2_0 23 36fac1d443SCristian Ciocaltea #define RESET_TVOUT 24 37fac1d443SCristian Ciocaltea #define RESET_HDMI 25 38fac1d443SCristian Ciocaltea #define RESET_HDCP2TX 26 39fac1d443SCristian Ciocaltea #define RESET_UART6 27 40fac1d443SCristian Ciocaltea #define RESET_UART0 28 41fac1d443SCristian Ciocaltea #define RESET_UART1 29 42fac1d443SCristian Ciocaltea #define RESET_UART2 30 43fac1d443SCristian Ciocaltea #define RESET_SPI0 31 44fac1d443SCristian Ciocaltea #define RESET_SPI1 32 45fac1d443SCristian Ciocaltea #define RESET_SPI2 33 46fac1d443SCristian Ciocaltea #define RESET_SPI3 34 47fac1d443SCristian Ciocaltea #define RESET_I2C0 35 48fac1d443SCristian Ciocaltea #define RESET_I2C1 36 49fac1d443SCristian Ciocaltea #define RESET_USB3 37 50fac1d443SCristian Ciocaltea #define RESET_UART3 38 51fac1d443SCristian Ciocaltea #define RESET_UART4 39 52fac1d443SCristian Ciocaltea #define RESET_UART5 40 53fac1d443SCristian Ciocaltea #define RESET_I2C2 41 54fac1d443SCristian Ciocaltea #define RESET_I2C3 42 55fac1d443SCristian Ciocaltea #define RESET_ETHERNET 43 56fac1d443SCristian Ciocaltea #define RESET_CHIPID 44 57fac1d443SCristian Ciocaltea #define RESET_USB2_1 45 58fac1d443SCristian Ciocaltea #define RESET_WD0RESET 46 59fac1d443SCristian Ciocaltea #define RESET_WD1RESET 47 60fac1d443SCristian Ciocaltea #define RESET_WD2RESET 48 61fac1d443SCristian Ciocaltea #define RESET_WD3RESET 49 62fac1d443SCristian Ciocaltea #define RESET_DBG0RESET 50 63fac1d443SCristian Ciocaltea #define RESET_DBG1RESET 51 64fac1d443SCristian Ciocaltea #define RESET_DBG2RESET 52 65fac1d443SCristian Ciocaltea #define RESET_DBG3RESET 53 66fac1d443SCristian Ciocaltea 67fac1d443SCristian Ciocaltea #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */ 68