18fd27fb4SRajan Vaja /* SPDX-License-Identifier: GPL-2.0 */ 28fd27fb4SRajan Vaja /* 38fd27fb4SRajan Vaja * Copyright (C) 2018 Xilinx, Inc. 48fd27fb4SRajan Vaja */ 58fd27fb4SRajan Vaja 68fd27fb4SRajan Vaja #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 78fd27fb4SRajan Vaja #define _DT_BINDINGS_ZYNQMP_POWER_H 88fd27fb4SRajan Vaja 9*ba4fde74STanmay Shah #define PD_RPU_0 7 10*ba4fde74STanmay Shah #define PD_RPU_1 8 11*ba4fde74STanmay Shah #define PD_R5_0_ATCM 15 12*ba4fde74STanmay Shah #define PD_R5_0_BTCM 16 13*ba4fde74STanmay Shah #define PD_R5_1_ATCM 17 14*ba4fde74STanmay Shah #define PD_R5_1_BTCM 18 158fd27fb4SRajan Vaja #define PD_USB_0 22 168fd27fb4SRajan Vaja #define PD_USB_1 23 178fd27fb4SRajan Vaja #define PD_TTC_0 24 188fd27fb4SRajan Vaja #define PD_TTC_1 25 198fd27fb4SRajan Vaja #define PD_TTC_2 26 208fd27fb4SRajan Vaja #define PD_TTC_3 27 218fd27fb4SRajan Vaja #define PD_SATA 28 228fd27fb4SRajan Vaja #define PD_ETH_0 29 238fd27fb4SRajan Vaja #define PD_ETH_1 30 248fd27fb4SRajan Vaja #define PD_ETH_2 31 258fd27fb4SRajan Vaja #define PD_ETH_3 32 268fd27fb4SRajan Vaja #define PD_UART_0 33 278fd27fb4SRajan Vaja #define PD_UART_1 34 288fd27fb4SRajan Vaja #define PD_SPI_0 35 298fd27fb4SRajan Vaja #define PD_SPI_1 36 308fd27fb4SRajan Vaja #define PD_I2C_0 37 318fd27fb4SRajan Vaja #define PD_I2C_1 38 328fd27fb4SRajan Vaja #define PD_SD_0 39 338fd27fb4SRajan Vaja #define PD_SD_1 40 348fd27fb4SRajan Vaja #define PD_DP 41 358fd27fb4SRajan Vaja #define PD_GDMA 42 368fd27fb4SRajan Vaja #define PD_ADMA 43 378fd27fb4SRajan Vaja #define PD_NAND 44 388fd27fb4SRajan Vaja #define PD_QSPI 45 398fd27fb4SRajan Vaja #define PD_GPIO 46 408fd27fb4SRajan Vaja #define PD_CAN_0 47 418fd27fb4SRajan Vaja #define PD_CAN_1 48 428fd27fb4SRajan Vaja #define PD_GPU 58 438fd27fb4SRajan Vaja #define PD_PCIE 59 448fd27fb4SRajan Vaja 458fd27fb4SRajan Vaja #endif 46