1*90715507SYoshihiro Shimoda /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*90715507SYoshihiro Shimoda /* 3*90715507SYoshihiro Shimoda * Copyright (C) 2022 Renesas Electronics Corp. 4*90715507SYoshihiro Shimoda */ 5*90715507SYoshihiro Shimoda #ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ 6*90715507SYoshihiro Shimoda #define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ 7*90715507SYoshihiro Shimoda 8*90715507SYoshihiro Shimoda /* 9*90715507SYoshihiro Shimoda * These power domain indices match the Power Domain Register Numbers (PDR) 10*90715507SYoshihiro Shimoda */ 11*90715507SYoshihiro Shimoda 12*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1E0D0C0 0 13*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1E0D0C1 1 14*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1E0D1C0 2 15*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1E0D1C1 3 16*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2E0D0 16 17*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2E0D1 17 18*90715507SYoshihiro Shimoda #define R8A779G0_PD_A3E0 20 19*90715507SYoshihiro Shimoda #define R8A779G0_PD_A33DGA 24 20*90715507SYoshihiro Shimoda #define R8A779G0_PD_A23DGB 25 21*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1DSP0 33 22*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2IMP01 34 23*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2PSC 35 24*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2CV0 36 25*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2CV1 37 26*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1CNN0 41 27*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2CN0 42 28*90715507SYoshihiro Shimoda #define R8A779G0_PD_A3IR 43 29*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1DSP1 45 30*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2IMP23 46 31*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2DMA 47 32*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2CV2 48 33*90715507SYoshihiro Shimoda #define R8A779G0_PD_A2CV3 49 34*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1DSP2 53 35*90715507SYoshihiro Shimoda #define R8A779G0_PD_A1DSP3 54 36*90715507SYoshihiro Shimoda #define R8A779G0_PD_A3VIP0 56 37*90715507SYoshihiro Shimoda #define R8A779G0_PD_A3VIP1 57 38*90715507SYoshihiro Shimoda #define R8A779G0_PD_A3VIP2 58 39*90715507SYoshihiro Shimoda #define R8A779G0_PD_A3ISP0 60 40*90715507SYoshihiro Shimoda #define R8A779G0_PD_A3ISP1 61 41*90715507SYoshihiro Shimoda 42*90715507SYoshihiro Shimoda /* Always-on power area */ 43*90715507SYoshihiro Shimoda #define R8A779G0_PD_ALWAYS_ON 64 44*90715507SYoshihiro Shimoda 45*90715507SYoshihiro Shimoda #endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/ 46