1c6e6eff4SRajendra Nayak /* SPDX-License-Identifier: GPL-2.0 */
2c6e6eff4SRajendra Nayak /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
3c6e6eff4SRajendra Nayak 
4c6e6eff4SRajendra Nayak #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
5c6e6eff4SRajendra Nayak #define _DT_BINDINGS_POWER_QCOM_RPMPD_H
6c6e6eff4SRajendra Nayak 
7c6e6eff4SRajendra Nayak /* SDM845 Power Domain Indexes */
8c6e6eff4SRajendra Nayak #define SDM845_EBI	0
9c6e6eff4SRajendra Nayak #define SDM845_MX	1
10c6e6eff4SRajendra Nayak #define SDM845_MX_AO	2
11c6e6eff4SRajendra Nayak #define SDM845_CX	3
12c6e6eff4SRajendra Nayak #define SDM845_CX_AO	4
13c6e6eff4SRajendra Nayak #define SDM845_LMX	5
14c6e6eff4SRajendra Nayak #define SDM845_LCX	6
15c6e6eff4SRajendra Nayak #define SDM845_GFX	7
16c6e6eff4SRajendra Nayak #define SDM845_MSS	8
17c6e6eff4SRajendra Nayak 
1818ec173dSSibi Sankar /* SM8150 Power Domain Indexes */
1918ec173dSSibi Sankar #define SM8150_MSS	0
2018ec173dSSibi Sankar #define SM8150_EBI	1
2118ec173dSSibi Sankar #define SM8150_LMX	2
2218ec173dSSibi Sankar #define SM8150_LCX	3
2318ec173dSSibi Sankar #define SM8150_GFX	4
2418ec173dSSibi Sankar #define SM8150_MX	5
2518ec173dSSibi Sankar #define SM8150_MX_AO	6
2618ec173dSSibi Sankar #define SM8150_CX	7
2718ec173dSSibi Sankar #define SM8150_CX_AO	8
2818ec173dSSibi Sankar #define SM8150_MMCX	9
2918ec173dSSibi Sankar #define SM8150_MMCX_AO	10
3018ec173dSSibi Sankar 
31c6e6eff4SRajendra Nayak /* SDM845 Power Domain performance levels */
32c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_RETENTION	16
33c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_MIN_SVS	48
34c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_LOW_SVS	64
35c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_SVS	128
36c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_SVS_L1	192
3718ec173dSSibi Sankar #define RPMH_REGULATOR_LEVEL_SVS_L2	224
38c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_NOM	256
39c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_NOM_L1	320
40c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_NOM_L2	336
41c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_TURBO	384
42c6e6eff4SRajendra Nayak #define RPMH_REGULATOR_LEVEL_TURBO_L1	416
43c6e6eff4SRajendra Nayak 
44b1d52244SAngeloGioacchino Del Regno /* MSM8976 Power Domain Indexes */
45b1d52244SAngeloGioacchino Del Regno #define MSM8976_VDDCX		0
46b1d52244SAngeloGioacchino Del Regno #define MSM8976_VDDCX_AO	1
47b1d52244SAngeloGioacchino Del Regno #define MSM8976_VDDCX_VFL	2
48b1d52244SAngeloGioacchino Del Regno #define MSM8976_VDDMX		3
49b1d52244SAngeloGioacchino Del Regno #define MSM8976_VDDMX_AO	4
50b1d52244SAngeloGioacchino Del Regno #define MSM8976_VDDMX_VFL	5
51b1d52244SAngeloGioacchino Del Regno 
52c6e6eff4SRajendra Nayak /* MSM8996 Power Domain Indexes */
53c6e6eff4SRajendra Nayak #define MSM8996_VDDCX		0
54c6e6eff4SRajendra Nayak #define MSM8996_VDDCX_AO	1
55c6e6eff4SRajendra Nayak #define MSM8996_VDDCX_VFC	2
56c6e6eff4SRajendra Nayak #define MSM8996_VDDMX		3
57c6e6eff4SRajendra Nayak #define MSM8996_VDDMX_AO	4
58c6e6eff4SRajendra Nayak #define MSM8996_VDDSSCX		5
59c6e6eff4SRajendra Nayak #define MSM8996_VDDSSCX_VFC	6
60c6e6eff4SRajendra Nayak 
61dec9a05aSSibi Sankar /* MSM8998 Power Domain Indexes */
62dec9a05aSSibi Sankar #define MSM8998_VDDCX		0
63dec9a05aSSibi Sankar #define MSM8998_VDDCX_AO	1
64dec9a05aSSibi Sankar #define MSM8998_VDDCX_VFL	2
65dec9a05aSSibi Sankar #define MSM8998_VDDMX		3
66dec9a05aSSibi Sankar #define MSM8998_VDDMX_AO	4
67dec9a05aSSibi Sankar #define MSM8998_VDDMX_VFL	5
68dec9a05aSSibi Sankar #define MSM8998_SSCCX		6
69dec9a05aSSibi Sankar #define MSM8998_SSCCX_VFL	7
70dec9a05aSSibi Sankar #define MSM8998_SSCMX		8
71dec9a05aSSibi Sankar #define MSM8998_SSCMX_VFL	9
72dec9a05aSSibi Sankar 
730cb93b15SBjorn Andersson /* QCS404 Power Domains */
740cb93b15SBjorn Andersson #define QCS404_VDDMX		0
750cb93b15SBjorn Andersson #define QCS404_VDDMX_AO		1
760cb93b15SBjorn Andersson #define QCS404_VDDMX_VFL	2
770cb93b15SBjorn Andersson #define QCS404_LPICX		3
780cb93b15SBjorn Andersson #define QCS404_LPICX_VFL	4
790cb93b15SBjorn Andersson #define QCS404_LPIMX		5
800cb93b15SBjorn Andersson #define QCS404_LPIMX_VFL	6
810cb93b15SBjorn Andersson 
820cb93b15SBjorn Andersson /* RPM SMD Power Domain performance levels */
830cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_RETENTION       16
840cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_RETENTION_PLUS  32
850cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_MIN_SVS         48
860cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_LOW_SVS         64
870cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_SVS             128
880cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_SVS_PLUS        192
890cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_NOM             256
900cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_NOM_PLUS        320
910cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_TURBO           384
920cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_TURBO_NO_CPR    416
934bc6aadbSAngelo G. Del Regno #define RPM_SMD_LEVEL_TURBO_HIGH      448
940cb93b15SBjorn Andersson #define RPM_SMD_LEVEL_BINNING         512
950cb93b15SBjorn Andersson 
96c6e6eff4SRajendra Nayak #endif
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