1*73c022e1SChun-Jie Chen /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2*73c022e1SChun-Jie Chen /*
3*73c022e1SChun-Jie Chen  * Copyright (c) 2021 MediaTek Inc.
4*73c022e1SChun-Jie Chen  * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5*73c022e1SChun-Jie Chen  */
6*73c022e1SChun-Jie Chen 
7*73c022e1SChun-Jie Chen #ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
8*73c022e1SChun-Jie Chen #define _DT_BINDINGS_POWER_MT8195_POWER_H
9*73c022e1SChun-Jie Chen 
10*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_PCIE_MAC_P0		0
11*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_PCIE_MAC_P1		1
12*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_PCIE_PHY		2
13*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY	3
14*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_CSI_RX_TOP		4
15*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_ETHER		5
16*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_ADSP		6
17*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_AUDIO		7
18*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_MFG0		8
19*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_MFG1		9
20*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_MFG2		10
21*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_MFG3		11
22*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_MFG4		12
23*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_MFG5		13
24*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_MFG6		14
25*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VPPSYS0		15
26*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VDOSYS0		16
27*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VPPSYS1		17
28*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VDOSYS1		18
29*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_DP_TX		19
30*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_EPD_TX		20
31*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_HDMI_TX		21
32*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_WPESYS		22
33*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VDEC0		23
34*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VDEC1		24
35*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VDEC2		25
36*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VENC		26
37*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_VENC_CORE1		27
38*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_IMG			28
39*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_DIP			29
40*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_IPE			30
41*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_CAM			31
42*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_CAM_RAWA		32
43*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_CAM_RAWB		33
44*73c022e1SChun-Jie Chen #define MT8195_POWER_DOMAIN_CAM_MRAW		34
45*73c022e1SChun-Jie Chen 
46*73c022e1SChun-Jie Chen #endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */
47