1*343106d9SWeiyi Lu /* SPDX-License-Identifier: GPL-2.0 2*343106d9SWeiyi Lu * 3*343106d9SWeiyi Lu * Copyright (c) 2020 MediaTek Inc. 4*343106d9SWeiyi Lu * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5*343106d9SWeiyi Lu */ 6*343106d9SWeiyi Lu 7*343106d9SWeiyi Lu #ifndef _DT_BINDINGS_POWER_MT8192_POWER_H 8*343106d9SWeiyi Lu #define _DT_BINDINGS_POWER_MT8192_POWER_H 9*343106d9SWeiyi Lu 10*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_AUDIO 0 11*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_CONN 1 12*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MFG0 2 13*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MFG1 3 14*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MFG2 4 15*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MFG3 5 16*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MFG4 6 17*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MFG5 7 18*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MFG6 8 19*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_DISP 9 20*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_IPE 10 21*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_ISP 11 22*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_ISP2 12 23*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_MDP 13 24*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_VENC 14 25*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_VDEC 15 26*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_VDEC2 16 27*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_CAM 17 28*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_CAM_RAWA 18 29*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_CAM_RAWB 19 30*343106d9SWeiyi Lu #define MT8192_POWER_DOMAIN_CAM_RAWC 20 31*343106d9SWeiyi Lu 32*343106d9SWeiyi Lu #endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ 33