1*94c0ded7SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 236c310f5SMars Cheng /* 336c310f5SMars Cheng * Copyright (c) 2017 MediaTek Inc. 436c310f5SMars Cheng * Author: Mars.C <mars.cheng@mediatek.com> 536c310f5SMars Cheng */ 636c310f5SMars Cheng 736c310f5SMars Cheng #ifndef _DT_BINDINGS_POWER_MT6797_POWER_H 836c310f5SMars Cheng #define _DT_BINDINGS_POWER_MT6797_POWER_H 936c310f5SMars Cheng 1036c310f5SMars Cheng #define MT6797_POWER_DOMAIN_VDEC 0 1136c310f5SMars Cheng #define MT6797_POWER_DOMAIN_VENC 1 1236c310f5SMars Cheng #define MT6797_POWER_DOMAIN_ISP 2 1336c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MM 3 1436c310f5SMars Cheng #define MT6797_POWER_DOMAIN_AUDIO 4 1536c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MFG_ASYNC 5 1636c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MFG 6 1736c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MFG_CORE0 7 1836c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MFG_CORE1 8 1936c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MFG_CORE2 9 2036c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MFG_CORE3 10 2136c310f5SMars Cheng #define MT6797_POWER_DOMAIN_MJC 11 2236c310f5SMars Cheng 2336c310f5SMars Cheng #endif /* _DT_BINDINGS_POWER_MT6797_POWER_H */ 24