1*440b075bSKrzysztof Kozlowski /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2165b5fb2SJianxin Pan /* 3165b5fb2SJianxin Pan * Copyright (c) 2019 Amlogic, Inc. 4165b5fb2SJianxin Pan * Author: Jianxin Pan <jianxin.pan@amlogic.com> 5165b5fb2SJianxin Pan */ 6165b5fb2SJianxin Pan 7165b5fb2SJianxin Pan #ifndef _DT_BINDINGS_MESON_A1_POWER_H 8165b5fb2SJianxin Pan #define _DT_BINDINGS_MESON_A1_POWER_H 9165b5fb2SJianxin Pan 10165b5fb2SJianxin Pan #define PWRC_DSPA_ID 8 11165b5fb2SJianxin Pan #define PWRC_DSPB_ID 9 12165b5fb2SJianxin Pan #define PWRC_UART_ID 10 13165b5fb2SJianxin Pan #define PWRC_DMC_ID 11 14165b5fb2SJianxin Pan #define PWRC_I2C_ID 12 15165b5fb2SJianxin Pan #define PWRC_PSRAM_ID 13 16165b5fb2SJianxin Pan #define PWRC_ACODEC_ID 14 17165b5fb2SJianxin Pan #define PWRC_AUDIO_ID 15 18165b5fb2SJianxin Pan #define PWRC_OTP_ID 16 19165b5fb2SJianxin Pan #define PWRC_DMA_ID 17 20165b5fb2SJianxin Pan #define PWRC_SD_EMMC_ID 18 21165b5fb2SJianxin Pan #define PWRC_RAMA_ID 19 22165b5fb2SJianxin Pan #define PWRC_RAMB_ID 20 23165b5fb2SJianxin Pan #define PWRC_IR_ID 21 24165b5fb2SJianxin Pan #define PWRC_SPICC_ID 22 25165b5fb2SJianxin Pan #define PWRC_SPIFC_ID 23 26165b5fb2SJianxin Pan #define PWRC_USB_ID 24 27165b5fb2SJianxin Pan #define PWRC_NIC_ID 25 28165b5fb2SJianxin Pan #define PWRC_PDMIN_ID 26 29165b5fb2SJianxin Pan #define PWRC_RSA_ID 27 30165b5fb2SJianxin Pan #define PWRC_MAX_ID 28 31165b5fb2SJianxin Pan 32165b5fb2SJianxin Pan #endif 33