1*ef641c44SSai Krishna Potthuri /* SPDX-License-Identifier: GPL-2.0 */ 2*ef641c44SSai Krishna Potthuri /* 3*ef641c44SSai Krishna Potthuri * MIO pin configuration defines for Xilinx Zynq 4*ef641c44SSai Krishna Potthuri * 5*ef641c44SSai Krishna Potthuri * Copyright (C) 2021 Xilinx, Inc. 6*ef641c44SSai Krishna Potthuri */ 7*ef641c44SSai Krishna Potthuri 8*ef641c44SSai Krishna Potthuri #ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H 9*ef641c44SSai Krishna Potthuri #define _DT_BINDINGS_PINCTRL_ZYNQ_H 10*ef641c44SSai Krishna Potthuri 11*ef641c44SSai Krishna Potthuri /* Configuration options for different power supplies */ 12*ef641c44SSai Krishna Potthuri #define IO_STANDARD_LVCMOS18 1 13*ef641c44SSai Krishna Potthuri #define IO_STANDARD_LVCMOS25 2 14*ef641c44SSai Krishna Potthuri #define IO_STANDARD_LVCMOS33 3 15*ef641c44SSai Krishna Potthuri #define IO_STANDARD_HSTL 4 16*ef641c44SSai Krishna Potthuri 17*ef641c44SSai Krishna Potthuri #endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */ 18