1b758df2eSLaxman Dewangan /* 2b758df2eSLaxman Dewangan * This header provides constants for Tegra pinctrl bindings. 3b758df2eSLaxman Dewangan * 4b758df2eSLaxman Dewangan * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 5b758df2eSLaxman Dewangan * 6b758df2eSLaxman Dewangan * Author: Laxman Dewangan <ldewangan@nvidia.com> 7b758df2eSLaxman Dewangan * 8b758df2eSLaxman Dewangan * This program is free software; you can redistribute it and/or modify it 9b758df2eSLaxman Dewangan * under the terms and conditions of the GNU General Public License, 10b758df2eSLaxman Dewangan * version 2, as published by the Free Software Foundation. 11b758df2eSLaxman Dewangan * 12b758df2eSLaxman Dewangan * This program is distributed in the hope it will be useful, but WITHOUT 13b758df2eSLaxman Dewangan * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14b758df2eSLaxman Dewangan * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15b758df2eSLaxman Dewangan * more details. 16b758df2eSLaxman Dewangan */ 17b758df2eSLaxman Dewangan 18b758df2eSLaxman Dewangan #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H 19b758df2eSLaxman Dewangan #define _DT_BINDINGS_PINCTRL_TEGRA_H 20b758df2eSLaxman Dewangan 21b758df2eSLaxman Dewangan /* 22b758df2eSLaxman Dewangan * Enable/disable for diffeent dt properties. This is applicable for 23b758df2eSLaxman Dewangan * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 24b758df2eSLaxman Dewangan * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 25b758df2eSLaxman Dewangan */ 26b758df2eSLaxman Dewangan #define TEGRA_PIN_DISABLE 0 27b758df2eSLaxman Dewangan #define TEGRA_PIN_ENABLE 1 28b758df2eSLaxman Dewangan 29b758df2eSLaxman Dewangan #define TEGRA_PIN_PULL_NONE 0 30b758df2eSLaxman Dewangan #define TEGRA_PIN_PULL_DOWN 1 31b758df2eSLaxman Dewangan #define TEGRA_PIN_PULL_UP 2 32b758df2eSLaxman Dewangan 33b758df2eSLaxman Dewangan /* Low power mode driver */ 34b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_8 0 35b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_4 1 36b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_2 2 37b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_1 3 38b758df2eSLaxman Dewangan 39b758df2eSLaxman Dewangan /* Rising/Falling slew rate */ 40b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_FASTEST 0 41b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_FAST 1 42b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_SLOW 2 43b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_SLOWEST 3 44b758df2eSLaxman Dewangan 45b758df2eSLaxman Dewangan #endif 46