1 /* 2 * Device Tree constants for the Texas Instruments DP83867 PHY 3 * 4 * Author: Dan Murphy <dmurphy@ti.com> 5 * 6 * Copyright: (C) 2015 Texas Instruments, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #ifndef _DT_BINDINGS_TI_DP83867_H 19 #define _DT_BINDINGS_TI_DP83867_H 20 21 /* PHY CTRL bits */ 22 #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 23 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 24 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 25 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 26 27 /* RGMIIDCTL internal delay for rx and tx */ 28 #define DP83867_RGMIIDCTL_250_PS 0x0 29 #define DP83867_RGMIIDCTL_500_PS 0x1 30 #define DP83867_RGMIIDCTL_750_PS 0x2 31 #define DP83867_RGMIIDCTL_1_NS 0x3 32 #define DP83867_RGMIIDCTL_1_25_NS 0x4 33 #define DP83867_RGMIIDCTL_1_50_NS 0x5 34 #define DP83867_RGMIIDCTL_1_75_NS 0x6 35 #define DP83867_RGMIIDCTL_2_00_NS 0x7 36 #define DP83867_RGMIIDCTL_2_25_NS 0x8 37 #define DP83867_RGMIIDCTL_2_50_NS 0x9 38 #define DP83867_RGMIIDCTL_2_75_NS 0xa 39 #define DP83867_RGMIIDCTL_3_00_NS 0xb 40 #define DP83867_RGMIIDCTL_3_25_NS 0xc 41 #define DP83867_RGMIIDCTL_3_50_NS 0xd 42 #define DP83867_RGMIIDCTL_3_75_NS 0xe 43 #define DP83867_RGMIIDCTL_4_00_NS 0xf 44 45 /* IO_MUX_CFG - Clock output selection */ 46 #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 47 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 48 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 49 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 50 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 51 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 52 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 53 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 54 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 55 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 56 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 57 #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 58 #define DP83867_CLK_O_SEL_REF_CLK 0xC 59 #endif 60