12a10154aSDan Murphy /* 22a10154aSDan Murphy * Device Tree constants for the Texas Instruments DP83867 PHY 32a10154aSDan Murphy * 42a10154aSDan Murphy * Author: Dan Murphy <dmurphy@ti.com> 52a10154aSDan Murphy * 62a10154aSDan Murphy * Copyright: (C) 2015 Texas Instruments, Inc. 72a10154aSDan Murphy * 82a10154aSDan Murphy * This program is free software; you can redistribute it and/or modify 92a10154aSDan Murphy * it under the terms of the GNU General Public License version 2 as 102a10154aSDan Murphy * published by the Free Software Foundation. 112a10154aSDan Murphy * 122a10154aSDan Murphy * This program is distributed in the hope that it will be useful, but 132a10154aSDan Murphy * WITHOUT ANY WARRANTY; without even the implied warranty of 142a10154aSDan Murphy * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 152a10154aSDan Murphy * General Public License for more details. 162a10154aSDan Murphy */ 172a10154aSDan Murphy 182a10154aSDan Murphy #ifndef _DT_BINDINGS_TI_DP83867_H 192a10154aSDan Murphy #define _DT_BINDINGS_TI_DP83867_H 202a10154aSDan Murphy 212a10154aSDan Murphy /* PHY CTRL bits */ 222a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 232a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 242a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 252a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 262a10154aSDan Murphy 272a10154aSDan Murphy /* RGMIIDCTL internal delay for rx and tx */ 282a10154aSDan Murphy #define DP83867_RGMIIDCTL_250_PS 0x0 292a10154aSDan Murphy #define DP83867_RGMIIDCTL_500_PS 0x1 302a10154aSDan Murphy #define DP83867_RGMIIDCTL_750_PS 0x2 312a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_NS 0x3 322a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_25_NS 0x4 332a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_50_NS 0x5 342a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_75_NS 0x6 352a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_00_NS 0x7 362a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_25_NS 0x8 372a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_50_NS 0x9 382a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_75_NS 0xa 392a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_00_NS 0xb 402a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_25_NS 0xc 412a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_50_NS 0xd 422a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_75_NS 0xe 432a10154aSDan Murphy #define DP83867_RGMIIDCTL_4_00_NS 0xf 442a10154aSDan Murphy 459708fb63SWadim Egorov /* IO_MUX_CFG - Clock output selection */ 469708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 479708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 489708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 499708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 509708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 519708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 529708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 539708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 549708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 559708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 569708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 579708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 589708fb63SWadim Egorov #define DP83867_CLK_O_SEL_REF_CLK 0xC 592a10154aSDan Murphy #endif 60