11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 22a10154aSDan Murphy /* 32a10154aSDan Murphy * Device Tree constants for the Texas Instruments DP83867 PHY 42a10154aSDan Murphy * 52a10154aSDan Murphy * Author: Dan Murphy <dmurphy@ti.com> 62a10154aSDan Murphy * 72a10154aSDan Murphy * Copyright: (C) 2015 Texas Instruments, Inc. 82a10154aSDan Murphy */ 92a10154aSDan Murphy 102a10154aSDan Murphy #ifndef _DT_BINDINGS_TI_DP83867_H 112a10154aSDan Murphy #define _DT_BINDINGS_TI_DP83867_H 122a10154aSDan Murphy 132a10154aSDan Murphy /* PHY CTRL bits */ 142a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 152a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 162a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 172a10154aSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 182a10154aSDan Murphy 192a10154aSDan Murphy /* RGMIIDCTL internal delay for rx and tx */ 202a10154aSDan Murphy #define DP83867_RGMIIDCTL_250_PS 0x0 212a10154aSDan Murphy #define DP83867_RGMIIDCTL_500_PS 0x1 222a10154aSDan Murphy #define DP83867_RGMIIDCTL_750_PS 0x2 232a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_NS 0x3 242a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_25_NS 0x4 252a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_50_NS 0x5 262a10154aSDan Murphy #define DP83867_RGMIIDCTL_1_75_NS 0x6 272a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_00_NS 0x7 282a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_25_NS 0x8 292a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_50_NS 0x9 302a10154aSDan Murphy #define DP83867_RGMIIDCTL_2_75_NS 0xa 312a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_00_NS 0xb 322a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_25_NS 0xc 332a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_50_NS 0xd 342a10154aSDan Murphy #define DP83867_RGMIIDCTL_3_75_NS 0xe 352a10154aSDan Murphy #define DP83867_RGMIIDCTL_4_00_NS 0xf 362a10154aSDan Murphy 379708fb63SWadim Egorov /* IO_MUX_CFG - Clock output selection */ 389708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 399708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 409708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 419708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 429708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 439708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 449708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 459708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 469708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 479708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 489708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 499708fb63SWadim Egorov #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 509708fb63SWadim Egorov #define DP83867_CLK_O_SEL_REF_CLK 0xC 512a10154aSDan Murphy /* Special flag to indicate clock should be off */ 52 #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF 53 #endif 54