1e5e3dea8SLaxman Dewangan /*
2e5e3dea8SLaxman Dewangan  * This header provides macros for MAXIM MAX77620 device bindings.
3e5e3dea8SLaxman Dewangan  *
4e5e3dea8SLaxman Dewangan  * Copyright (c) 2016, NVIDIA Corporation.
5e5e3dea8SLaxman Dewangan  * Author: Laxman Dewangan <ldewangan@nvidia.com>
6e5e3dea8SLaxman Dewangan  */
7e5e3dea8SLaxman Dewangan 
8e5e3dea8SLaxman Dewangan #ifndef _DT_BINDINGS_MFD_MAX77620_H
9e5e3dea8SLaxman Dewangan #define _DT_BINDINGS_MFD_MAX77620_H
10e5e3dea8SLaxman Dewangan 
11e5e3dea8SLaxman Dewangan /* MAX77620 interrupts */
12e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_TOP_GLBL		0 /* Low-Battery */
13e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_TOP_SD		1 /* SD power fail */
14e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_TOP_LDO		2 /* LDO power fail */
15e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_TOP_GPIO		3 /* GPIO internal int to MAX77620 */
16e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_TOP_RTC		4 /* RTC */
17e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_TOP_32K		5 /* 32kHz oscillator */
18e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_TOP_ONOFF		6 /* ON/OFF oscillator */
19e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_LBT_MBATLOW	7 /* Thermal alarm status, > 120C */
20e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_LBT_TJALRM1	8 /* Thermal alarm status, > 120C */
21e5e3dea8SLaxman Dewangan #define MAX77620_IRQ_LBT_TJALRM2	9 /* Thermal alarm status, > 140C */
22e5e3dea8SLaxman Dewangan 
23e5e3dea8SLaxman Dewangan /* FPS event source */
24e5e3dea8SLaxman Dewangan #define MAX77620_FPS_EVENT_SRC_EN0		0
25e5e3dea8SLaxman Dewangan #define MAX77620_FPS_EVENT_SRC_EN1		1
26e5e3dea8SLaxman Dewangan #define MAX77620_FPS_EVENT_SRC_SW		2
27e5e3dea8SLaxman Dewangan 
28e5e3dea8SLaxman Dewangan /* Device state when FPS event LOW  */
29e5e3dea8SLaxman Dewangan #define MAX77620_FPS_INACTIVE_STATE_SLEEP	0
30e5e3dea8SLaxman Dewangan #define MAX77620_FPS_INACTIVE_STATE_LOW_POWER	1
31e5e3dea8SLaxman Dewangan 
32e5e3dea8SLaxman Dewangan /* FPS source */
33e5e3dea8SLaxman Dewangan #define MAX77620_FPS_SRC_0			0
34e5e3dea8SLaxman Dewangan #define MAX77620_FPS_SRC_1			1
35e5e3dea8SLaxman Dewangan #define MAX77620_FPS_SRC_2			2
36e5e3dea8SLaxman Dewangan #define MAX77620_FPS_SRC_NONE			3
37e5e3dea8SLaxman Dewangan #define MAX77620_FPS_SRC_DEF			4
38e5e3dea8SLaxman Dewangan 
39e5e3dea8SLaxman Dewangan #endif
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