1 /* 2 * This header provides macros for ams AS3722 device bindings. 3 * 4 * Copyright (c) 2013, NVIDIA Corporation. 5 * 6 * Author: Laxman Dewangan <ldewangan@nvidia.com> 7 * 8 */ 9 10 #ifndef __DT_BINDINGS_AS3722_H__ 11 #define __DT_BINDINGS_AS3722_H__ 12 13 /* External control pins */ 14 #define AS3722_EXT_CONTROL_PIN_ENABLE1 1 15 #define AS3722_EXT_CONTROL_PIN_ENABLE2 2 16 #define AS3722_EXT_CONTROL_PIN_ENABLE3 3 17 18 /* Interrupt numbers for AS3722 */ 19 #define AS3722_IRQ_LID 0 20 #define AS3722_IRQ_ACOK 1 21 #define AS3722_IRQ_ENABLE1 2 22 #define AS3722_IRQ_OCCUR_ALARM_SD0 3 23 #define AS3722_IRQ_ONKEY_LONG_PRESS 4 24 #define AS3722_IRQ_ONKEY 5 25 #define AS3722_IRQ_OVTMP 6 26 #define AS3722_IRQ_LOWBAT 7 27 #define AS3722_IRQ_SD0_LV 8 28 #define AS3722_IRQ_SD1_LV 9 29 #define AS3722_IRQ_SD2_LV 10 30 #define AS3722_IRQ_PWM1_OV_PROT 11 31 #define AS3722_IRQ_PWM2_OV_PROT 12 32 #define AS3722_IRQ_ENABLE2 13 33 #define AS3722_IRQ_SD6_LV 14 34 #define AS3722_IRQ_RTC_REP 15 35 #define AS3722_IRQ_RTC_ALARM 16 36 #define AS3722_IRQ_GPIO1 17 37 #define AS3722_IRQ_GPIO2 18 38 #define AS3722_IRQ_GPIO3 19 39 #define AS3722_IRQ_GPIO4 20 40 #define AS3722_IRQ_GPIO5 21 41 #define AS3722_IRQ_WATCHDOG 22 42 #define AS3722_IRQ_ENABLE3 23 43 #define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 44 #define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 45 #define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 46 #define AS3722_IRQ_TEMP_SD0_ALARM 27 47 #define AS3722_IRQ_TEMP_SD1_ALARM 28 48 #define AS3722_IRQ_TEMP_SD6_ALARM 29 49 #define AS3722_IRQ_OCCUR_ALARM_SD6 30 50 #define AS3722_IRQ_ADC 31 51 52 #endif /* __DT_BINDINGS_AS3722_H__ */ 53