189184651SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H 289184651SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA30_MC_H 389184651SThierry Reding 489184651SThierry Reding #define TEGRA_SWGROUP_PTC 0 589184651SThierry Reding #define TEGRA_SWGROUP_DC 1 689184651SThierry Reding #define TEGRA_SWGROUP_DCB 2 789184651SThierry Reding #define TEGRA_SWGROUP_EPP 3 889184651SThierry Reding #define TEGRA_SWGROUP_G2 4 989184651SThierry Reding #define TEGRA_SWGROUP_MPE 5 1089184651SThierry Reding #define TEGRA_SWGROUP_VI 6 1189184651SThierry Reding #define TEGRA_SWGROUP_AFI 7 1289184651SThierry Reding #define TEGRA_SWGROUP_AVPC 8 1389184651SThierry Reding #define TEGRA_SWGROUP_NV 9 1489184651SThierry Reding #define TEGRA_SWGROUP_NV2 10 1589184651SThierry Reding #define TEGRA_SWGROUP_HDA 11 1689184651SThierry Reding #define TEGRA_SWGROUP_HC 12 1789184651SThierry Reding #define TEGRA_SWGROUP_PPCS 13 1889184651SThierry Reding #define TEGRA_SWGROUP_SATA 14 1989184651SThierry Reding #define TEGRA_SWGROUP_VDE 15 2089184651SThierry Reding #define TEGRA_SWGROUP_MPCORELP 16 2189184651SThierry Reding #define TEGRA_SWGROUP_MPCORE 17 2289184651SThierry Reding #define TEGRA_SWGROUP_ISP 18 2389184651SThierry Reding 2489184651SThierry Reding #endif 25