1c3859c14SThierry Reding /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 240efe139SSameer Pujar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3c3859c14SThierry Reding 4c3859c14SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H 5c3859c14SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA234_MC_H 6c3859c14SThierry Reding 7c3859c14SThierry Reding /* special clients */ 8c3859c14SThierry Reding #define TEGRA234_SID_INVALID 0x00 9c3859c14SThierry Reding #define TEGRA234_SID_PASSTHROUGH 0x7f 10c3859c14SThierry Reding 1140efe139SSameer Pujar /* NISO0 stream IDs */ 1240efe139SSameer Pujar #define TEGRA234_SID_APE 0x02 1307d74390SMohan Kumar #define TEGRA234_SID_HDA 0x03 14*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE0 0x12 15*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE4 0x13 16*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE5 0x14 17*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE6 0x15 18*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE9 0x1f 19c3859c14SThierry Reding 20c3859c14SThierry Reding /* NISO1 stream IDs */ 21c3859c14SThierry Reding #define TEGRA234_SID_SDMMC4 0x02 22*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE1 0x05 23*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE2 0x06 24*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE3 0x07 25*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE7 0x08 26*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE8 0x09 27*a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE10 0x0b 28c3859c14SThierry Reding #define TEGRA234_SID_BPMP 0x10 29c3859c14SThierry Reding 30c3859c14SThierry Reding /* 31c3859c14SThierry Reding * memory client IDs 32c3859c14SThierry Reding */ 33c3859c14SThierry Reding 3407d74390SMohan Kumar /* High-definition audio (HDA) read clients */ 3507d74390SMohan Kumar #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 36*a4ad66daSVidya Sagar /* PCIE6 read clients */ 37*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 38*a4ad66daSVidya Sagar /* PCIE6 write clients */ 39*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 40*a4ad66daSVidya Sagar /* PCIE7 read clients */ 41*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a 42*a4ad66daSVidya Sagar /* PCIE7 write clients */ 43*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 44*a4ad66daSVidya Sagar /* PCIE8 read clients */ 45*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 4607d74390SMohan Kumar /* High-definition audio (HDA) write clients */ 4707d74390SMohan Kumar #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 48*a4ad66daSVidya Sagar /* PCIE8 write clients */ 49*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b 50*a4ad66daSVidya Sagar /* PCIE9 read clients */ 51*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c 52*a4ad66daSVidya Sagar /* PCIE6r1 read clients */ 53*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d 54*a4ad66daSVidya Sagar /* PCIE9 write clients */ 55*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e 56*a4ad66daSVidya Sagar /* PCIE10 read clients */ 57*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f 58*a4ad66daSVidya Sagar /* PCIE10 write clients */ 59*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 60*a4ad66daSVidya Sagar /* PCIE10r1 read clients */ 61*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 62*a4ad66daSVidya Sagar /* PCIE7r1 read clients */ 63*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 64c3859c14SThierry Reding /* sdmmcd memory read client */ 65c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 66c3859c14SThierry Reding /* sdmmcd memory write client */ 67c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 68c3859c14SThierry Reding /* BPMP read client */ 69c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 70c3859c14SThierry Reding /* BPMP write client */ 71c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 72c3859c14SThierry Reding /* BPMPDMA read client */ 73c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 74c3859c14SThierry Reding /* BPMPDMA write client */ 75c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 7640efe139SSameer Pujar /* APEDMA read client */ 7740efe139SSameer Pujar #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f 7840efe139SSameer Pujar /* APEDMA write client */ 7940efe139SSameer Pujar #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 80*a4ad66daSVidya Sagar /* PCIE0 read clients */ 81*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 82*a4ad66daSVidya Sagar /* PCIE0 write clients */ 83*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 84*a4ad66daSVidya Sagar /* PCIE1 read clients */ 85*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda 86*a4ad66daSVidya Sagar /* PCIE1 write clients */ 87*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb 88*a4ad66daSVidya Sagar /* PCIE2 read clients */ 89*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc 90*a4ad66daSVidya Sagar /* PCIE2 write clients */ 91*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd 92*a4ad66daSVidya Sagar /* PCIE3 read clients */ 93*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde 94*a4ad66daSVidya Sagar /* PCIE3 write clients */ 95*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf 96*a4ad66daSVidya Sagar /* PCIE4 read clients */ 97*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 98*a4ad66daSVidya Sagar /* PCIE4 write clients */ 99*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 100*a4ad66daSVidya Sagar /* PCIE5 read clients */ 101*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 102*a4ad66daSVidya Sagar /* PCIE5 write clients */ 103*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 104*a4ad66daSVidya Sagar /* PCIE5r1 read clients */ 105*a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef 106c3859c14SThierry Reding 107c3859c14SThierry Reding #endif 108