1c3859c14SThierry Reding /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 240efe139SSameer Pujar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3c3859c14SThierry Reding 4c3859c14SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H 5c3859c14SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA234_MC_H 6c3859c14SThierry Reding 7c3859c14SThierry Reding /* special clients */ 8c3859c14SThierry Reding #define TEGRA234_SID_INVALID 0x00 9c3859c14SThierry Reding #define TEGRA234_SID_PASSTHROUGH 0x7f 10c3859c14SThierry Reding 1140efe139SSameer Pujar /* NISO0 stream IDs */ 1240efe139SSameer Pujar #define TEGRA234_SID_APE 0x02 1307d74390SMohan Kumar #define TEGRA234_SID_HDA 0x03 14*3ffb20f5SAkhil R #define TEGRA234_SID_GPCDMA 0x04 15a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE0 0x12 16a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE4 0x13 17a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE5 0x14 18a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE6 0x15 19a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE9 0x1f 20c3859c14SThierry Reding 21c3859c14SThierry Reding /* NISO1 stream IDs */ 22c3859c14SThierry Reding #define TEGRA234_SID_SDMMC4 0x02 23a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE1 0x05 24a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE2 0x06 25a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE3 0x07 26a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE7 0x08 27a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE8 0x09 28a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE10 0x0b 29c3859c14SThierry Reding #define TEGRA234_SID_BPMP 0x10 30c3859c14SThierry Reding 31c3859c14SThierry Reding /* 32c3859c14SThierry Reding * memory client IDs 33c3859c14SThierry Reding */ 34c3859c14SThierry Reding 3507d74390SMohan Kumar /* High-definition audio (HDA) read clients */ 3607d74390SMohan Kumar #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 37a4ad66daSVidya Sagar /* PCIE6 read clients */ 38a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 39a4ad66daSVidya Sagar /* PCIE6 write clients */ 40a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 41a4ad66daSVidya Sagar /* PCIE7 read clients */ 42a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a 43a4ad66daSVidya Sagar /* PCIE7 write clients */ 44a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 45a4ad66daSVidya Sagar /* PCIE8 read clients */ 46a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 4707d74390SMohan Kumar /* High-definition audio (HDA) write clients */ 4807d74390SMohan Kumar #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 49a4ad66daSVidya Sagar /* PCIE8 write clients */ 50a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b 51a4ad66daSVidya Sagar /* PCIE9 read clients */ 52a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c 53a4ad66daSVidya Sagar /* PCIE6r1 read clients */ 54a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d 55a4ad66daSVidya Sagar /* PCIE9 write clients */ 56a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e 57a4ad66daSVidya Sagar /* PCIE10 read clients */ 58a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f 59a4ad66daSVidya Sagar /* PCIE10 write clients */ 60a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 61a4ad66daSVidya Sagar /* PCIE10r1 read clients */ 62a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 63a4ad66daSVidya Sagar /* PCIE7r1 read clients */ 64a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 65c3859c14SThierry Reding /* sdmmcd memory read client */ 66c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 67c3859c14SThierry Reding /* sdmmcd memory write client */ 68c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 69c3859c14SThierry Reding /* BPMP read client */ 70c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 71c3859c14SThierry Reding /* BPMP write client */ 72c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 73c3859c14SThierry Reding /* BPMPDMA read client */ 74c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 75c3859c14SThierry Reding /* BPMPDMA write client */ 76c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 7740efe139SSameer Pujar /* APEDMA read client */ 7840efe139SSameer Pujar #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f 7940efe139SSameer Pujar /* APEDMA write client */ 8040efe139SSameer Pujar #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 81a4ad66daSVidya Sagar /* PCIE0 read clients */ 82a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 83a4ad66daSVidya Sagar /* PCIE0 write clients */ 84a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 85a4ad66daSVidya Sagar /* PCIE1 read clients */ 86a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda 87a4ad66daSVidya Sagar /* PCIE1 write clients */ 88a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb 89a4ad66daSVidya Sagar /* PCIE2 read clients */ 90a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc 91a4ad66daSVidya Sagar /* PCIE2 write clients */ 92a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd 93a4ad66daSVidya Sagar /* PCIE3 read clients */ 94a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde 95a4ad66daSVidya Sagar /* PCIE3 write clients */ 96a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf 97a4ad66daSVidya Sagar /* PCIE4 read clients */ 98a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 99a4ad66daSVidya Sagar /* PCIE4 write clients */ 100a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 101a4ad66daSVidya Sagar /* PCIE5 read clients */ 102a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 103a4ad66daSVidya Sagar /* PCIE5 write clients */ 104a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 105a4ad66daSVidya Sagar /* PCIE5r1 read clients */ 106a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef 107c3859c14SThierry Reding 108c3859c14SThierry Reding #endif 109