1c3859c14SThierry Reding /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 240efe139SSameer Pujar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3c3859c14SThierry Reding 4c3859c14SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H 5c3859c14SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA234_MC_H 6c3859c14SThierry Reding 7c3859c14SThierry Reding /* special clients */ 8c3859c14SThierry Reding #define TEGRA234_SID_INVALID 0x00 9c3859c14SThierry Reding #define TEGRA234_SID_PASSTHROUGH 0x7f 10c3859c14SThierry Reding 1140efe139SSameer Pujar /* NISO0 stream IDs */ 1240efe139SSameer Pujar #define TEGRA234_SID_APE 0x02 1307d74390SMohan Kumar #define TEGRA234_SID_HDA 0x03 143ffb20f5SAkhil R #define TEGRA234_SID_GPCDMA 0x04 15833f5a7eSThierry Reding #define TEGRA234_SID_MGBE 0x06 16a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE0 0x12 17a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE4 0x13 18a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE5 0x14 19a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE6 0x15 20a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE9 0x1f 21833f5a7eSThierry Reding #define TEGRA234_SID_MGBE_VF1 0x49 22833f5a7eSThierry Reding #define TEGRA234_SID_MGBE_VF2 0x4a 23833f5a7eSThierry Reding #define TEGRA234_SID_MGBE_VF3 0x4b 24c3859c14SThierry Reding 25c3859c14SThierry Reding /* NISO1 stream IDs */ 26c3859c14SThierry Reding #define TEGRA234_SID_SDMMC4 0x02 27a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE1 0x05 28a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE2 0x06 29a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE3 0x07 30a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE7 0x08 31a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE8 0x09 32a4ad66daSVidya Sagar #define TEGRA234_SID_PCIE10 0x0b 33c3859c14SThierry Reding #define TEGRA234_SID_BPMP 0x10 3463a6ef23SMikko Perttunen #define TEGRA234_SID_HOST1X 0x27 35*0e2b014eSMikko Perttunen #define TEGRA234_SID_NVDEC 0x29 3663a6ef23SMikko Perttunen #define TEGRA234_SID_VIC 0x34 37c3859c14SThierry Reding 38cc99f95dSMikko Perttunen /* Shared stream IDs */ 39cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX0 0x35 40cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX1 0x36 41cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX2 0x37 42cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX3 0x38 43cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX4 0x39 44cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX5 0x3a 45cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX6 0x3b 46cc99f95dSMikko Perttunen #define TEGRA234_SID_HOST1X_CTX7 0x3c 47cc99f95dSMikko Perttunen 48c3859c14SThierry Reding /* 49c3859c14SThierry Reding * memory client IDs 50c3859c14SThierry Reding */ 51c3859c14SThierry Reding 5207d74390SMohan Kumar /* High-definition audio (HDA) read clients */ 5307d74390SMohan Kumar #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 5463a6ef23SMikko Perttunen #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 55a4ad66daSVidya Sagar /* PCIE6 read clients */ 56a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 57a4ad66daSVidya Sagar /* PCIE6 write clients */ 58a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 59a4ad66daSVidya Sagar /* PCIE7 read clients */ 60a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a 61a4ad66daSVidya Sagar /* PCIE7 write clients */ 62a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 63a4ad66daSVidya Sagar /* PCIE8 read clients */ 64a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 6507d74390SMohan Kumar /* High-definition audio (HDA) write clients */ 6607d74390SMohan Kumar #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 67a4ad66daSVidya Sagar /* PCIE8 write clients */ 68a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b 69a4ad66daSVidya Sagar /* PCIE9 read clients */ 70a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c 71a4ad66daSVidya Sagar /* PCIE6r1 read clients */ 72a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d 73a4ad66daSVidya Sagar /* PCIE9 write clients */ 74a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e 75a4ad66daSVidya Sagar /* PCIE10 read clients */ 76a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f 77a4ad66daSVidya Sagar /* PCIE10 write clients */ 78a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 79a4ad66daSVidya Sagar /* PCIE10r1 read clients */ 80a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 81a4ad66daSVidya Sagar /* PCIE7r1 read clients */ 82a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 83833f5a7eSThierry Reding /* MGBE0 read client */ 84833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 85833f5a7eSThierry Reding /* MGBEB read client */ 86833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 87833f5a7eSThierry Reding /* MGBEC read client */ 88833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a 89833f5a7eSThierry Reding /* MGBED read client */ 90833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b 91833f5a7eSThierry Reding /* MGBE0 write client */ 92833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c 93833f5a7eSThierry Reding /* MGBEB write client */ 94833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f 95833f5a7eSThierry Reding /* MGBEC write client */ 96833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 97c3859c14SThierry Reding /* sdmmcd memory read client */ 98c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 99833f5a7eSThierry Reding /* MGBED write client */ 100833f5a7eSThierry Reding #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 101c3859c14SThierry Reding /* sdmmcd memory write client */ 102c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 10363a6ef23SMikko Perttunen #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c 10463a6ef23SMikko Perttunen #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d 105*0e2b014eSMikko Perttunen #define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 106*0e2b014eSMikko Perttunen #define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 107c3859c14SThierry Reding /* BPMP read client */ 108c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 109c3859c14SThierry Reding /* BPMP write client */ 110c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 111c3859c14SThierry Reding /* BPMPDMA read client */ 112c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 113c3859c14SThierry Reding /* BPMPDMA write client */ 114c3859c14SThierry Reding #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 11540efe139SSameer Pujar /* APEDMA read client */ 11640efe139SSameer Pujar #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f 11740efe139SSameer Pujar /* APEDMA write client */ 11840efe139SSameer Pujar #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 119a4ad66daSVidya Sagar /* PCIE0 read clients */ 120a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 121a4ad66daSVidya Sagar /* PCIE0 write clients */ 122a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 123a4ad66daSVidya Sagar /* PCIE1 read clients */ 124a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda 125a4ad66daSVidya Sagar /* PCIE1 write clients */ 126a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb 127a4ad66daSVidya Sagar /* PCIE2 read clients */ 128a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc 129a4ad66daSVidya Sagar /* PCIE2 write clients */ 130a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd 131a4ad66daSVidya Sagar /* PCIE3 read clients */ 132a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde 133a4ad66daSVidya Sagar /* PCIE3 write clients */ 134a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf 135a4ad66daSVidya Sagar /* PCIE4 read clients */ 136a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 137a4ad66daSVidya Sagar /* PCIE4 write clients */ 138a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 139a4ad66daSVidya Sagar /* PCIE5 read clients */ 140a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 141a4ad66daSVidya Sagar /* PCIE5 write clients */ 142a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 143a4ad66daSVidya Sagar /* PCIE5r1 read clients */ 144a4ad66daSVidya Sagar #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef 145c3859c14SThierry Reding 146c3859c14SThierry Reding #endif 147