1588c43a7SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
2588c43a7SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA210_MC_H
3588c43a7SThierry Reding 
4588c43a7SThierry Reding #define TEGRA_SWGROUP_PTC	0
5588c43a7SThierry Reding #define TEGRA_SWGROUP_DC	1
6588c43a7SThierry Reding #define TEGRA_SWGROUP_DCB	2
7588c43a7SThierry Reding #define TEGRA_SWGROUP_AFI	3
8588c43a7SThierry Reding #define TEGRA_SWGROUP_AVPC	4
9588c43a7SThierry Reding #define TEGRA_SWGROUP_HDA	5
10588c43a7SThierry Reding #define TEGRA_SWGROUP_HC	6
11588c43a7SThierry Reding #define TEGRA_SWGROUP_NVENC	7
12588c43a7SThierry Reding #define TEGRA_SWGROUP_PPCS	8
13588c43a7SThierry Reding #define TEGRA_SWGROUP_SATA	9
14588c43a7SThierry Reding #define TEGRA_SWGROUP_MPCORE	10
15588c43a7SThierry Reding #define TEGRA_SWGROUP_ISP2	11
16588c43a7SThierry Reding #define TEGRA_SWGROUP_XUSB_HOST	12
17588c43a7SThierry Reding #define TEGRA_SWGROUP_XUSB_DEV	13
18588c43a7SThierry Reding #define TEGRA_SWGROUP_ISP2B	14
19588c43a7SThierry Reding #define TEGRA_SWGROUP_TSEC	15
20588c43a7SThierry Reding #define TEGRA_SWGROUP_A9AVP	16
21588c43a7SThierry Reding #define TEGRA_SWGROUP_GPU	17
22588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC1A	18
23588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC2A	19
24588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC3A	20
25588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC4A	21
26588c43a7SThierry Reding #define TEGRA_SWGROUP_VIC	22
27588c43a7SThierry Reding #define TEGRA_SWGROUP_VI	23
28588c43a7SThierry Reding #define TEGRA_SWGROUP_NVDEC	24
29588c43a7SThierry Reding #define TEGRA_SWGROUP_APE	25
30588c43a7SThierry Reding #define TEGRA_SWGROUP_NVJPG	26
31588c43a7SThierry Reding #define TEGRA_SWGROUP_SE	27
32588c43a7SThierry Reding #define TEGRA_SWGROUP_AXIAP	28
33588c43a7SThierry Reding #define TEGRA_SWGROUP_ETR	29
34588c43a7SThierry Reding #define TEGRA_SWGROUP_TSECB	30
35588c43a7SThierry Reding 
36588c43a7SThierry Reding #endif
37