1a213f9f1SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H 2a213f9f1SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA194_MC_H 3a213f9f1SThierry Reding 4a213f9f1SThierry Reding /* special clients */ 5a213f9f1SThierry Reding #define TEGRA194_SID_INVALID 0x00 6a213f9f1SThierry Reding #define TEGRA194_SID_PASSTHROUGH 0x7f 7a213f9f1SThierry Reding 8a213f9f1SThierry Reding /* host1x clients */ 9a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X 0x01 10a213f9f1SThierry Reding #define TEGRA194_SID_CSI 0x02 11a213f9f1SThierry Reding #define TEGRA194_SID_VIC 0x03 12a213f9f1SThierry Reding #define TEGRA194_SID_VI 0x04 13a213f9f1SThierry Reding #define TEGRA194_SID_ISP 0x05 14a213f9f1SThierry Reding #define TEGRA194_SID_NVDEC 0x06 15a213f9f1SThierry Reding #define TEGRA194_SID_NVENC 0x07 16a213f9f1SThierry Reding #define TEGRA194_SID_NVJPG 0x08 17a213f9f1SThierry Reding #define TEGRA194_SID_NVDISPLAY 0x09 18a213f9f1SThierry Reding #define TEGRA194_SID_TSEC 0x0a 19a213f9f1SThierry Reding #define TEGRA194_SID_TSECB 0x0b 20a213f9f1SThierry Reding #define TEGRA194_SID_SE 0x0c 21a213f9f1SThierry Reding #define TEGRA194_SID_SE1 0x0d 22a213f9f1SThierry Reding #define TEGRA194_SID_SE2 0x0e 23a213f9f1SThierry Reding #define TEGRA194_SID_SE3 0x0f 24a213f9f1SThierry Reding 25a213f9f1SThierry Reding /* GPU clients */ 26a213f9f1SThierry Reding #define TEGRA194_SID_GPU 0x10 27a213f9f1SThierry Reding 28a213f9f1SThierry Reding /* other SoC clients */ 29a213f9f1SThierry Reding #define TEGRA194_SID_AFI 0x11 30a213f9f1SThierry Reding #define TEGRA194_SID_HDA 0x12 31a213f9f1SThierry Reding #define TEGRA194_SID_ETR 0x13 32a213f9f1SThierry Reding #define TEGRA194_SID_EQOS 0x14 33a213f9f1SThierry Reding #define TEGRA194_SID_UFSHC 0x15 34a213f9f1SThierry Reding #define TEGRA194_SID_AON 0x16 35a213f9f1SThierry Reding #define TEGRA194_SID_SDMMC4 0x17 36a213f9f1SThierry Reding #define TEGRA194_SID_SDMMC3 0x18 37a213f9f1SThierry Reding #define TEGRA194_SID_SDMMC2 0x19 38a213f9f1SThierry Reding #define TEGRA194_SID_SDMMC1 0x1a 39a213f9f1SThierry Reding #define TEGRA194_SID_XUSB_HOST 0x1b 40a213f9f1SThierry Reding #define TEGRA194_SID_XUSB_DEV 0x1c 41a213f9f1SThierry Reding #define TEGRA194_SID_SATA 0x1d 42a213f9f1SThierry Reding #define TEGRA194_SID_APE 0x1e 43a213f9f1SThierry Reding #define TEGRA194_SID_SCE 0x1f 44a213f9f1SThierry Reding 45a213f9f1SThierry Reding /* GPC DMA clients */ 46a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_0 0x20 47a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_1 0x21 48a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_2 0x22 49a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_3 0x23 50a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_4 0x24 51a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_5 0x25 52a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_6 0x26 53a213f9f1SThierry Reding #define TEGRA194_SID_GPCDMA_7 0x27 54a213f9f1SThierry Reding 55a213f9f1SThierry Reding /* APE DMA clients */ 56a213f9f1SThierry Reding #define TEGRA194_SID_APE_1 0x28 57a213f9f1SThierry Reding #define TEGRA194_SID_APE_2 0x29 58a213f9f1SThierry Reding 59a213f9f1SThierry Reding /* camera RTCPU */ 60a213f9f1SThierry Reding #define TEGRA194_SID_RCE 0x2a 61a213f9f1SThierry Reding 62a213f9f1SThierry Reding /* camera RTCPU on host1x address space */ 63a213f9f1SThierry Reding #define TEGRA194_SID_RCE_1X 0x2b 64a213f9f1SThierry Reding 65a213f9f1SThierry Reding /* APE DMA clients */ 66a213f9f1SThierry Reding #define TEGRA194_SID_APE_3 0x2c 67a213f9f1SThierry Reding 68a213f9f1SThierry Reding /* camera RTCPU running on APE */ 69a213f9f1SThierry Reding #define TEGRA194_SID_APE_CAM 0x2d 70a213f9f1SThierry Reding #define TEGRA194_SID_APE_CAM_1X 0x2e 71a213f9f1SThierry Reding 72a213f9f1SThierry Reding #define TEGRA194_SID_RCE_RM 0x2f 73a213f9f1SThierry Reding #define TEGRA194_SID_VI_FALCON 0x30 74a213f9f1SThierry Reding #define TEGRA194_SID_ISP_FALCON 0x31 75a213f9f1SThierry Reding 76a213f9f1SThierry Reding /* 77a213f9f1SThierry Reding * The BPMP has its SID value hardcoded in the firmware. Changing it requires 78a213f9f1SThierry Reding * considerable effort. 79a213f9f1SThierry Reding */ 80a213f9f1SThierry Reding #define TEGRA194_SID_BPMP 0x32 81a213f9f1SThierry Reding 82a213f9f1SThierry Reding /* for SMMU tests */ 83a213f9f1SThierry Reding #define TEGRA194_SID_SMMU_TEST 0x33 84a213f9f1SThierry Reding 85a213f9f1SThierry Reding /* host1x virtualization channels */ 86a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX0 0x38 87a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX1 0x39 88a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX2 0x3a 89a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX3 0x3b 90a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX4 0x3c 91a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX5 0x3d 92a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX6 0x3e 93a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_CTX7 0x3f 94a213f9f1SThierry Reding 95a213f9f1SThierry Reding /* host1x command buffers */ 96a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM0 0x40 97a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM1 0x41 98a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM2 0x42 99a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM3 0x43 100a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM4 0x44 101a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM5 0x45 102a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM6 0x46 103a213f9f1SThierry Reding #define TEGRA194_SID_HOST1X_VM7 0x47 104a213f9f1SThierry Reding 105a213f9f1SThierry Reding /* SE data buffers */ 106a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM0 0x48 107a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM1 0x49 108a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM2 0x4a 109a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM3 0x4b 110a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM4 0x4c 111a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM5 0x4d 112a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM6 0x4e 113a213f9f1SThierry Reding #define TEGRA194_SID_SE_VM7 0x4f 114a213f9f1SThierry Reding 115a213f9f1SThierry Reding #define TEGRA194_SID_MIU 0x50 116a213f9f1SThierry Reding 117a213f9f1SThierry Reding #define TEGRA194_SID_NVDLA0 0x51 118a213f9f1SThierry Reding #define TEGRA194_SID_NVDLA1 0x52 119a213f9f1SThierry Reding 120a213f9f1SThierry Reding #define TEGRA194_SID_PVA0 0x53 121a213f9f1SThierry Reding #define TEGRA194_SID_PVA1 0x54 122a213f9f1SThierry Reding #define TEGRA194_SID_NVENC1 0x55 123a213f9f1SThierry Reding #define TEGRA194_SID_PCIE0 0x56 124a213f9f1SThierry Reding #define TEGRA194_SID_PCIE1 0x57 125a213f9f1SThierry Reding #define TEGRA194_SID_PCIE2 0x58 126a213f9f1SThierry Reding #define TEGRA194_SID_PCIE3 0x59 127a213f9f1SThierry Reding #define TEGRA194_SID_PCIE4 0x5a 128a213f9f1SThierry Reding #define TEGRA194_SID_PCIE5 0x5b 129a213f9f1SThierry Reding #define TEGRA194_SID_NVDEC1 0x5c 130a213f9f1SThierry Reding 131a213f9f1SThierry Reding #define TEGRA194_SID_XUSB_VF0 0x5d 132a213f9f1SThierry Reding #define TEGRA194_SID_XUSB_VF1 0x5e 133a213f9f1SThierry Reding #define TEGRA194_SID_XUSB_VF2 0x5f 134a213f9f1SThierry Reding #define TEGRA194_SID_XUSB_VF3 0x60 135a213f9f1SThierry Reding 136a213f9f1SThierry Reding #define TEGRA194_SID_RCE_VM3 0x61 137a213f9f1SThierry Reding #define TEGRA194_SID_VI_VM2 0x62 138a213f9f1SThierry Reding #define TEGRA194_SID_VI_VM3 0x63 139a213f9f1SThierry Reding #define TEGRA194_SID_RCE_SERVER 0x64 140a213f9f1SThierry Reding 141a213f9f1SThierry Reding /* 142a213f9f1SThierry Reding * memory client IDs 143a213f9f1SThierry Reding */ 144a213f9f1SThierry Reding 145a213f9f1SThierry Reding /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 146a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PTCR 0x00 147a213f9f1SThierry Reding /* MSS internal memqual MIU7 read clients */ 148a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 149a213f9f1SThierry Reding /* MSS internal memqual MIU7 write clients */ 150a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 151a213f9f1SThierry Reding /* High-definition audio (HDA) read clients */ 152a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_HDAR 0x15 153a213f9f1SThierry Reding /* Host channel data read clients */ 154a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 155a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c 156a213f9f1SThierry Reding /* SATA read clients */ 157a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SATAR 0x1f 158a213f9f1SThierry Reding /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 159a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 160a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b 161a213f9f1SThierry Reding /* High-definition audio (HDA) write clients */ 162a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_HDAW 0x35 163a213f9f1SThierry Reding /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 164a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 165a213f9f1SThierry Reding /* SATA write clients */ 166a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SATAW 0x3d 167a213f9f1SThierry Reding /* ISP read client for Crossbar A */ 168a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 169a213f9f1SThierry Reding /* ISP read client 1 for Crossbar A */ 170a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 171a213f9f1SThierry Reding /* ISP Write client for Crossbar A */ 172a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 173a213f9f1SThierry Reding /* ISP Write client Crossbar B */ 174a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 175a213f9f1SThierry Reding /* XUSB_HOST read clients */ 176a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a 177a213f9f1SThierry Reding /* XUSB_HOST write clients */ 178a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b 179a213f9f1SThierry Reding /* XUSB read clients */ 180a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c 181a213f9f1SThierry Reding /* XUSB_DEV write clients */ 182a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d 183a213f9f1SThierry Reding /* sdmmca memory read client */ 184a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 185a213f9f1SThierry Reding /* sdmmc memory read client */ 186a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 187a213f9f1SThierry Reding /* sdmmcd memory read client */ 188a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 189a213f9f1SThierry Reding /* sdmmca memory write client */ 190a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 191a213f9f1SThierry Reding /* sdmmc memory write client */ 192a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 193a213f9f1SThierry Reding /* sdmmcd memory write client */ 194a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 195a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c 196a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d 197a213f9f1SThierry Reding /* VI Write client */ 198a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_VIW 0x72 199a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 200a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 201a213f9f1SThierry Reding /* Audio Processing (APE) engine read clients */ 202a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_APER 0x7a 203a213f9f1SThierry Reding /* Audio Processing (APE) engine write clients */ 204a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_APEW 0x7b 205a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e 206a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f 207a213f9f1SThierry Reding /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ 208a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 209a213f9f1SThierry Reding /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ 210a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 211a213f9f1SThierry Reding /* ETR read clients */ 212a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ETRR 0x84 213a213f9f1SThierry Reding /* ETR write clients */ 214a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ETRW 0x85 215a213f9f1SThierry Reding /* AXI Switch read client */ 216a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AXISR 0x8c 217a213f9f1SThierry Reding /* AXI Switch write client */ 218a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AXISW 0x8d 219a213f9f1SThierry Reding /* EQOS read client */ 220a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e 221a213f9f1SThierry Reding /* EQOS write client */ 222a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f 223a213f9f1SThierry Reding /* UFSHC read client */ 224a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 225a213f9f1SThierry Reding /* UFSHC write client */ 226a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 227a213f9f1SThierry Reding /* NVDISPLAY read client */ 228a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 229a213f9f1SThierry Reding /* BPMP read client */ 230a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 231a213f9f1SThierry Reding /* BPMP write client */ 232a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 233a213f9f1SThierry Reding /* BPMPDMA read client */ 234a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 235a213f9f1SThierry Reding /* BPMPDMA write client */ 236a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 237a213f9f1SThierry Reding /* AON read client */ 238a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AONR 0x97 239a213f9f1SThierry Reding /* AON write client */ 240a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AONW 0x98 241a213f9f1SThierry Reding /* AONDMA read client */ 242a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 243a213f9f1SThierry Reding /* AONDMA write client */ 244a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a 245a213f9f1SThierry Reding /* SCE read client */ 246a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SCER 0x9b 247a213f9f1SThierry Reding /* SCE write client */ 248a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SCEW 0x9c 249a213f9f1SThierry Reding /* SCEDMA read client */ 250a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d 251a213f9f1SThierry Reding /* SCEDMA write client */ 252a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e 253a213f9f1SThierry Reding /* APEDMA read client */ 254a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f 255a213f9f1SThierry Reding /* APEDMA write client */ 256a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 257a213f9f1SThierry Reding /* NVDISPLAY read client instance 2 */ 258a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 259a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 260a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 261a213f9f1SThierry Reding /* MSS internal memqual MIU0 read clients */ 262a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 263a213f9f1SThierry Reding /* MSS internal memqual MIU0 write clients */ 264a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 265a213f9f1SThierry Reding /* MSS internal memqual MIU1 read clients */ 266a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 267a213f9f1SThierry Reding /* MSS internal memqual MIU1 write clients */ 268a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 269a213f9f1SThierry Reding /* MSS internal memqual MIU2 read clients */ 270a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU2R 0xae 271a213f9f1SThierry Reding /* MSS internal memqual MIU2 write clients */ 272a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf 273a213f9f1SThierry Reding /* MSS internal memqual MIU3 read clients */ 274a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 275a213f9f1SThierry Reding /* MSS internal memqual MIU3 write clients */ 276a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 277a213f9f1SThierry Reding /* MSS internal memqual MIU4 read clients */ 278a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 279a213f9f1SThierry Reding /* MSS internal memqual MIU4 write clients */ 280a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 281a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 282a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 283a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 284a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 285a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 286a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 287a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL2R 0xba 288a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb 289a213f9f1SThierry Reding /* VI FLACON read clients */ 290a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc 291a213f9f1SThierry Reding /* VIFAL write clients */ 292a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd 293a213f9f1SThierry Reding /* DLA0ARDA read clients */ 294a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe 295a213f9f1SThierry Reding /* DLA0 Falcon read clients */ 296a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf 297a213f9f1SThierry Reding /* DLA0 write clients */ 298a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 299a213f9f1SThierry Reding /* DLA0 write clients */ 300a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 301a213f9f1SThierry Reding /* DLA1ARDA read clients */ 302a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 303a213f9f1SThierry Reding /* DLA1 Falcon read clients */ 304a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 305a213f9f1SThierry Reding /* DLA1 write clients */ 306a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 307a213f9f1SThierry Reding /* DLA1 write clients */ 308a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 309a213f9f1SThierry Reding /* PVA0RDA read clients */ 310a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 311a213f9f1SThierry Reding /* PVA0RDB read clients */ 312a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 313a213f9f1SThierry Reding /* PVA0RDC read clients */ 314a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 315a213f9f1SThierry Reding /* PVA0WRA write clients */ 316a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 317a213f9f1SThierry Reding /* PVA0WRB write clients */ 318a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca 319a213f9f1SThierry Reding /* PVA0WRC write clients */ 320a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb 321a213f9f1SThierry Reding /* PVA1RDA read clients */ 322a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc 323a213f9f1SThierry Reding /* PVA1RDB read clients */ 324a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd 325a213f9f1SThierry Reding /* PVA1RDC read clients */ 326a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce 327a213f9f1SThierry Reding /* PVA1WRA write clients */ 328a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf 329a213f9f1SThierry Reding /* PVA1WRB write clients */ 330a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 331a213f9f1SThierry Reding /* PVA1WRC write clients */ 332a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 333a213f9f1SThierry Reding /* RCE read client */ 334a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_RCER 0xd2 335a213f9f1SThierry Reding /* RCE write client */ 336a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 337a213f9f1SThierry Reding /* RCEDMA read client */ 338a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 339a213f9f1SThierry Reding /* RCEDMA write client */ 340a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 341a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 342a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 343a213f9f1SThierry Reding /* PCIE0 read clients */ 344a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 345a213f9f1SThierry Reding /* PCIE0 write clients */ 346a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 347a213f9f1SThierry Reding /* PCIE1 read clients */ 348a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda 349a213f9f1SThierry Reding /* PCIE1 write clients */ 350a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb 351a213f9f1SThierry Reding /* PCIE2 read clients */ 352a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc 353a213f9f1SThierry Reding /* PCIE2 write clients */ 354a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd 355a213f9f1SThierry Reding /* PCIE3 read clients */ 356a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde 357a213f9f1SThierry Reding /* PCIE3 write clients */ 358a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf 359a213f9f1SThierry Reding /* PCIE4 read clients */ 360a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 361a213f9f1SThierry Reding /* PCIE4 write clients */ 362a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 363a213f9f1SThierry Reding /* PCIE5 read clients */ 364a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 365a213f9f1SThierry Reding /* PCIE5 write clients */ 366a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 367a213f9f1SThierry Reding /* ISP read client 1 for Crossbar A */ 368a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 369a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 370a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 371a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 372a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 373a213f9f1SThierry Reding /* DLA0ARDA1 read clients */ 374a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 375a213f9f1SThierry Reding /* DLA1ARDA1 read clients */ 376a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea 377a213f9f1SThierry Reding /* PVA0RDA1 read clients */ 378a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb 379a213f9f1SThierry Reding /* PVA0RDB1 read clients */ 380a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec 381a213f9f1SThierry Reding /* PVA1RDA1 read clients */ 382a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed 383a213f9f1SThierry Reding /* PVA1RDB1 read clients */ 384a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee 385a213f9f1SThierry Reding /* PCIE5r1 read clients */ 386a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef 387a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 388a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 389a213f9f1SThierry Reding /* ISP read client for Crossbar A */ 390a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 391a213f9f1SThierry Reding /* PCIE0 read clients */ 392a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 393a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 394a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 395a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 396a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 397a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 398a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 399a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa 400a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb 401a213f9f1SThierry Reding /* MSS internal memqual MIU5 read clients */ 402a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc 403a213f9f1SThierry Reding /* MSS internal memqual MIU5 write clients */ 404a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd 405a213f9f1SThierry Reding /* MSS internal memqual MIU6 read clients */ 406a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe 407a213f9f1SThierry Reding /* MSS internal memqual MIU6 write clients */ 408a213f9f1SThierry Reding #define TEGRA194_MEMORY_CLIENT_MIU6W 0xff 409a213f9f1SThierry Reding 410a213f9f1SThierry Reding #endif 411