1029ab5eaSThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H 2029ab5eaSThierry Reding #define DT_BINDINGS_MEMORY_TEGRA186_MC_H 3029ab5eaSThierry Reding 4029ab5eaSThierry Reding /* special clients */ 5029ab5eaSThierry Reding #define TEGRA186_SID_INVALID 0x00 6029ab5eaSThierry Reding #define TEGRA186_SID_PASSTHROUGH 0x7f 7029ab5eaSThierry Reding 8029ab5eaSThierry Reding /* host1x clients */ 9029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X 0x01 10029ab5eaSThierry Reding #define TEGRA186_SID_CSI 0x02 11029ab5eaSThierry Reding #define TEGRA186_SID_VIC 0x03 12029ab5eaSThierry Reding #define TEGRA186_SID_VI 0x04 13029ab5eaSThierry Reding #define TEGRA186_SID_ISP 0x05 14029ab5eaSThierry Reding #define TEGRA186_SID_NVDEC 0x06 15029ab5eaSThierry Reding #define TEGRA186_SID_NVENC 0x07 16029ab5eaSThierry Reding #define TEGRA186_SID_NVJPG 0x08 17029ab5eaSThierry Reding #define TEGRA186_SID_NVDISPLAY 0x09 18029ab5eaSThierry Reding #define TEGRA186_SID_TSEC 0x0a 19029ab5eaSThierry Reding #define TEGRA186_SID_TSECB 0x0b 20029ab5eaSThierry Reding #define TEGRA186_SID_SE 0x0c 21029ab5eaSThierry Reding #define TEGRA186_SID_SE1 0x0d 22029ab5eaSThierry Reding #define TEGRA186_SID_SE2 0x0e 23029ab5eaSThierry Reding #define TEGRA186_SID_SE3 0x0f 24029ab5eaSThierry Reding 25029ab5eaSThierry Reding /* GPU clients */ 26029ab5eaSThierry Reding #define TEGRA186_SID_GPU 0x10 27029ab5eaSThierry Reding 28029ab5eaSThierry Reding /* other SoC clients */ 29029ab5eaSThierry Reding #define TEGRA186_SID_AFI 0x11 30029ab5eaSThierry Reding #define TEGRA186_SID_HDA 0x12 31029ab5eaSThierry Reding #define TEGRA186_SID_ETR 0x13 32029ab5eaSThierry Reding #define TEGRA186_SID_EQOS 0x14 33029ab5eaSThierry Reding #define TEGRA186_SID_UFSHC 0x15 34029ab5eaSThierry Reding #define TEGRA186_SID_AON 0x16 35029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC4 0x17 36029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC3 0x18 37029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC2 0x19 38029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC1 0x1a 39029ab5eaSThierry Reding #define TEGRA186_SID_XUSB_HOST 0x1b 40029ab5eaSThierry Reding #define TEGRA186_SID_XUSB_DEV 0x1c 41029ab5eaSThierry Reding #define TEGRA186_SID_SATA 0x1d 42029ab5eaSThierry Reding #define TEGRA186_SID_APE 0x1e 43029ab5eaSThierry Reding #define TEGRA186_SID_SCE 0x1f 44029ab5eaSThierry Reding 45029ab5eaSThierry Reding /* GPC DMA clients */ 46029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_0 0x20 47029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_1 0x21 48029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_2 0x22 49029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_3 0x23 50029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_4 0x24 51029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_5 0x25 52029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_6 0x26 53029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_7 0x27 54029ab5eaSThierry Reding 55029ab5eaSThierry Reding /* APE DMA clients */ 56029ab5eaSThierry Reding #define TEGRA186_SID_APE_1 0x28 57029ab5eaSThierry Reding #define TEGRA186_SID_APE_2 0x29 58029ab5eaSThierry Reding 59029ab5eaSThierry Reding /* camera RTCPU */ 60029ab5eaSThierry Reding #define TEGRA186_SID_RCE 0x2a 61029ab5eaSThierry Reding 62029ab5eaSThierry Reding /* camera RTCPU on host1x address space */ 63029ab5eaSThierry Reding #define TEGRA186_SID_RCE_1X 0x2b 64029ab5eaSThierry Reding 65029ab5eaSThierry Reding /* APE DMA clients */ 66029ab5eaSThierry Reding #define TEGRA186_SID_APE_3 0x2c 67029ab5eaSThierry Reding 68029ab5eaSThierry Reding /* camera RTCPU running on APE */ 69029ab5eaSThierry Reding #define TEGRA186_SID_APE_CAM 0x2d 70029ab5eaSThierry Reding #define TEGRA186_SID_APE_CAM_1X 0x2e 71029ab5eaSThierry Reding 72029ab5eaSThierry Reding /* 73029ab5eaSThierry Reding * The BPMP has its SID value hardcoded in the firmware. Changing it requires 74029ab5eaSThierry Reding * considerable effort. 75029ab5eaSThierry Reding */ 76029ab5eaSThierry Reding #define TEGRA186_SID_BPMP 0x32 77029ab5eaSThierry Reding 78029ab5eaSThierry Reding /* for SMMU tests */ 79029ab5eaSThierry Reding #define TEGRA186_SID_SMMU_TEST 0x33 80029ab5eaSThierry Reding 81029ab5eaSThierry Reding /* host1x virtualization channels */ 82029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX0 0x38 83029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX1 0x39 84029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX2 0x3a 85029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX3 0x3b 86029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX4 0x3c 87029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX5 0x3d 88029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX6 0x3e 89029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX7 0x3f 90029ab5eaSThierry Reding 91029ab5eaSThierry Reding /* host1x command buffers */ 92029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM0 0x40 93029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM1 0x41 94029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM2 0x42 95029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM3 0x43 96029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM4 0x44 97029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM5 0x45 98029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM6 0x46 99029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM7 0x47 100029ab5eaSThierry Reding 101029ab5eaSThierry Reding /* SE data buffers */ 102029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM0 0x48 103029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM1 0x49 104029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM2 0x4a 105029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM3 0x4b 106029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM4 0x4c 107029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM5 0x4d 108029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM6 0x4e 109029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM7 0x4f 110029ab5eaSThierry Reding 111029ab5eaSThierry Reding #endif 112