189184651SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H 289184651SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA124_MC_H 389184651SThierry Reding 489184651SThierry Reding #define TEGRA_SWGROUP_PTC 0 589184651SThierry Reding #define TEGRA_SWGROUP_DC 1 689184651SThierry Reding #define TEGRA_SWGROUP_DCB 2 789184651SThierry Reding #define TEGRA_SWGROUP_AFI 3 889184651SThierry Reding #define TEGRA_SWGROUP_AVPC 4 989184651SThierry Reding #define TEGRA_SWGROUP_HDA 5 1089184651SThierry Reding #define TEGRA_SWGROUP_HC 6 1189184651SThierry Reding #define TEGRA_SWGROUP_MSENC 7 1289184651SThierry Reding #define TEGRA_SWGROUP_PPCS 8 1389184651SThierry Reding #define TEGRA_SWGROUP_SATA 9 1489184651SThierry Reding #define TEGRA_SWGROUP_VDE 10 1589184651SThierry Reding #define TEGRA_SWGROUP_MPCORELP 11 1689184651SThierry Reding #define TEGRA_SWGROUP_MPCORE 12 1789184651SThierry Reding #define TEGRA_SWGROUP_ISP2 13 1889184651SThierry Reding #define TEGRA_SWGROUP_XUSB_HOST 14 1989184651SThierry Reding #define TEGRA_SWGROUP_XUSB_DEV 15 2089184651SThierry Reding #define TEGRA_SWGROUP_ISP2B 16 2189184651SThierry Reding #define TEGRA_SWGROUP_TSEC 17 2289184651SThierry Reding #define TEGRA_SWGROUP_A9AVP 18 2389184651SThierry Reding #define TEGRA_SWGROUP_GPU 19 2489184651SThierry Reding #define TEGRA_SWGROUP_SDMMC1A 20 2589184651SThierry Reding #define TEGRA_SWGROUP_SDMMC2A 21 2689184651SThierry Reding #define TEGRA_SWGROUP_SDMMC3A 22 2789184651SThierry Reding #define TEGRA_SWGROUP_SDMMC4A 23 2889184651SThierry Reding #define TEGRA_SWGROUP_VIC 24 2989184651SThierry Reding #define TEGRA_SWGROUP_VI 25 3089184651SThierry Reding 3189184651SThierry Reding #endif 32