1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 289184651SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H 389184651SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA124_MC_H 489184651SThierry Reding 589184651SThierry Reding #define TEGRA_SWGROUP_PTC 0 689184651SThierry Reding #define TEGRA_SWGROUP_DC 1 789184651SThierry Reding #define TEGRA_SWGROUP_DCB 2 889184651SThierry Reding #define TEGRA_SWGROUP_AFI 3 989184651SThierry Reding #define TEGRA_SWGROUP_AVPC 4 1089184651SThierry Reding #define TEGRA_SWGROUP_HDA 5 1189184651SThierry Reding #define TEGRA_SWGROUP_HC 6 1289184651SThierry Reding #define TEGRA_SWGROUP_MSENC 7 1389184651SThierry Reding #define TEGRA_SWGROUP_PPCS 8 1489184651SThierry Reding #define TEGRA_SWGROUP_SATA 9 1589184651SThierry Reding #define TEGRA_SWGROUP_VDE 10 1689184651SThierry Reding #define TEGRA_SWGROUP_MPCORELP 11 1789184651SThierry Reding #define TEGRA_SWGROUP_MPCORE 12 1889184651SThierry Reding #define TEGRA_SWGROUP_ISP2 13 1989184651SThierry Reding #define TEGRA_SWGROUP_XUSB_HOST 14 2089184651SThierry Reding #define TEGRA_SWGROUP_XUSB_DEV 15 2189184651SThierry Reding #define TEGRA_SWGROUP_ISP2B 16 2289184651SThierry Reding #define TEGRA_SWGROUP_TSEC 17 2389184651SThierry Reding #define TEGRA_SWGROUP_A9AVP 18 2489184651SThierry Reding #define TEGRA_SWGROUP_GPU 19 2589184651SThierry Reding #define TEGRA_SWGROUP_SDMMC1A 20 2689184651SThierry Reding #define TEGRA_SWGROUP_SDMMC2A 21 2789184651SThierry Reding #define TEGRA_SWGROUP_SDMMC3A 22 2889184651SThierry Reding #define TEGRA_SWGROUP_SDMMC4A 23 2989184651SThierry Reding #define TEGRA_SWGROUP_VIC 24 3089184651SThierry Reding #define TEGRA_SWGROUP_VI 25 3189184651SThierry Reding 325c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_AFI 0 335c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_AVPC 1 345c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_DC 2 355c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_DCB 3 365c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_HC 4 375c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_HDA 5 385c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_ISP2 6 395c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_MPCORE 7 405c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_MPCORELP 8 415c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_MSENC 9 425c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_PPCS 10 435c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SATA 11 445c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_VDE 12 455c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_VI 13 465c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_VIC 14 475c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_XUSB_HOST 15 485c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_XUSB_DEV 16 495c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_TSEC 17 505c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC1 18 515c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC2 19 525c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC3 20 535c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC4 21 545c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_ISP2B 22 555c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_GPU 23 565c8d08f3SDmitry Osipenko 5789184651SThierry Reding #endif 58