1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 289184651SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H 389184651SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA124_MC_H 489184651SThierry Reding 589184651SThierry Reding #define TEGRA_SWGROUP_PTC 0 689184651SThierry Reding #define TEGRA_SWGROUP_DC 1 789184651SThierry Reding #define TEGRA_SWGROUP_DCB 2 889184651SThierry Reding #define TEGRA_SWGROUP_AFI 3 989184651SThierry Reding #define TEGRA_SWGROUP_AVPC 4 1089184651SThierry Reding #define TEGRA_SWGROUP_HDA 5 1189184651SThierry Reding #define TEGRA_SWGROUP_HC 6 1289184651SThierry Reding #define TEGRA_SWGROUP_MSENC 7 1389184651SThierry Reding #define TEGRA_SWGROUP_PPCS 8 1489184651SThierry Reding #define TEGRA_SWGROUP_SATA 9 1589184651SThierry Reding #define TEGRA_SWGROUP_VDE 10 1689184651SThierry Reding #define TEGRA_SWGROUP_MPCORELP 11 1789184651SThierry Reding #define TEGRA_SWGROUP_MPCORE 12 1889184651SThierry Reding #define TEGRA_SWGROUP_ISP2 13 1989184651SThierry Reding #define TEGRA_SWGROUP_XUSB_HOST 14 2089184651SThierry Reding #define TEGRA_SWGROUP_XUSB_DEV 15 2189184651SThierry Reding #define TEGRA_SWGROUP_ISP2B 16 2289184651SThierry Reding #define TEGRA_SWGROUP_TSEC 17 2389184651SThierry Reding #define TEGRA_SWGROUP_A9AVP 18 2489184651SThierry Reding #define TEGRA_SWGROUP_GPU 19 2589184651SThierry Reding #define TEGRA_SWGROUP_SDMMC1A 20 2689184651SThierry Reding #define TEGRA_SWGROUP_SDMMC2A 21 2789184651SThierry Reding #define TEGRA_SWGROUP_SDMMC3A 22 2889184651SThierry Reding #define TEGRA_SWGROUP_SDMMC4A 23 2989184651SThierry Reding #define TEGRA_SWGROUP_VIC 24 3089184651SThierry Reding #define TEGRA_SWGROUP_VI 25 3189184651SThierry Reding 325c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_AFI 0 335c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_AVPC 1 345c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_DC 2 355c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_DCB 3 365c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_HC 4 375c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_HDA 5 385c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_ISP2 6 395c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_MPCORE 7 405c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_MPCORELP 8 415c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_MSENC 9 425c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_PPCS 10 435c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SATA 11 445c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_VDE 12 455c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_VI 13 465c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_VIC 14 475c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_XUSB_HOST 15 485c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_XUSB_DEV 16 495c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_TSEC 17 505c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC1 18 515c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC2 19 525c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC3 20 535c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_SDMMC4 21 545c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_ISP2B 22 555c8d08f3SDmitry Osipenko #define TEGRA124_MC_RESET_GPU 23 565c8d08f3SDmitry Osipenko 57*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_PTCR 0 58*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAY0A 1 59*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAY0AB 2 60*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAY0B 3 61*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAY0BB 4 62*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAY0C 5 63*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAY0CB 6 64*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_AFIR 14 65*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_AVPCARM7R 15 66*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAYHC 16 67*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAYHCB 17 68*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_HDAR 21 69*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_HOST1XDMAR 22 70*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_HOST1XR 23 71*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_MSENCSRD 28 72*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_PPCSAHBDMAR 29 73*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_PPCSAHBSLVR 30 74*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SATAR 31 75*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDEBSEVR 34 76*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDEMBER 35 77*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDEMCER 36 78*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDETPER 37 79*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_MPCORELPR 38 80*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_MPCORER 39 81*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_MSENCSWR 43 82*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_AFIW 49 83*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_AVPCARM7W 50 84*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_HDAW 53 85*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_HOST1XW 54 86*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_MPCORELPW 56 87*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_MPCOREW 57 88*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_PPCSAHBDMAW 59 89*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_PPCSAHBSLVW 60 90*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SATAW 61 91*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDEBSEVW 62 92*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDEDBGW 63 93*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDEMBEW 64 94*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VDETPMW 65 95*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_ISPRA 68 96*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_ISPWA 70 97*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_ISPWB 71 98*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_XUSB_HOSTR 74 99*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_XUSB_HOSTW 75 100*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_XUSB_DEVR 76 101*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_XUSB_DEVW 77 102*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_ISPRAB 78 103*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_ISPWAB 80 104*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_ISPWBB 81 105*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_TSECSRD 84 106*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_TSECSWR 85 107*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_A9AVPSCR 86 108*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_A9AVPSCW 87 109*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_GPUSRD 88 110*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_GPUSWR 89 111*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAYT 90 112*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCRA 96 113*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCRAA 97 114*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCR 98 115*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCRAB 99 116*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCWA 100 117*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCWAA 101 118*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCW 102 119*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_SDMMCWAB 103 120*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VICSRD 108 121*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VICSWR 109 122*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_VIW 114 123*24a7eaeaSDmitry Osipenko #define TEGRA124_MC_DISPLAYD 115 124*24a7eaeaSDmitry Osipenko 12589184651SThierry Reding #endif 126