189184651SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H 289184651SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA114_MC_H 389184651SThierry Reding 489184651SThierry Reding #define TEGRA_SWGROUP_PTC 0 589184651SThierry Reding #define TEGRA_SWGROUP_DC 1 689184651SThierry Reding #define TEGRA_SWGROUP_DCB 2 789184651SThierry Reding #define TEGRA_SWGROUP_EPP 3 889184651SThierry Reding #define TEGRA_SWGROUP_G2 4 989184651SThierry Reding #define TEGRA_SWGROUP_AVPC 5 1089184651SThierry Reding #define TEGRA_SWGROUP_NV 6 1189184651SThierry Reding #define TEGRA_SWGROUP_HDA 7 1289184651SThierry Reding #define TEGRA_SWGROUP_HC 8 1389184651SThierry Reding #define TEGRA_SWGROUP_MSENC 9 1489184651SThierry Reding #define TEGRA_SWGROUP_PPCS 10 1589184651SThierry Reding #define TEGRA_SWGROUP_VDE 11 1689184651SThierry Reding #define TEGRA_SWGROUP_MPCORELP 12 1789184651SThierry Reding #define TEGRA_SWGROUP_MPCORE 13 1889184651SThierry Reding #define TEGRA_SWGROUP_VI 14 1989184651SThierry Reding #define TEGRA_SWGROUP_ISP 15 2089184651SThierry Reding #define TEGRA_SWGROUP_XUSB_HOST 16 2189184651SThierry Reding #define TEGRA_SWGROUP_XUSB_DEV 17 2289184651SThierry Reding #define TEGRA_SWGROUP_EMUCIF 18 2389184651SThierry Reding #define TEGRA_SWGROUP_TSEC 19 2489184651SThierry Reding 2589184651SThierry Reding #endif 26