15cf482f2SYong Wu /* SPDX-License-Identifier: GPL-2.0-only */ 25cf482f2SYong Wu /* 35cf482f2SYong Wu * Copyright (c) 2020 MediaTek Inc. 45cf482f2SYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 55cf482f2SYong Wu */ 65cf482f2SYong Wu #ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ 75cf482f2SYong Wu #define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ 85cf482f2SYong Wu 9ca49a4b4SYong Wu #define MTK_LARB_NR_MAX 32 105cf482f2SYong Wu 115cf482f2SYong Wu #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) 12ca49a4b4SYong Wu #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) 135cf482f2SYong Wu #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) 145cf482f2SYong Wu 15*dc1d9934SYong Wu #define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port) 16*dc1d9934SYong Wu 175cf482f2SYong Wu #endif 18