1*6625ffb9SYong Wu /* SPDX-License-Identifier: GPL-2.0-only */ 2*6625ffb9SYong Wu /* 3*6625ffb9SYong Wu * Copyright (c) 2022 MediaTek Inc. 4*6625ffb9SYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5*6625ffb9SYong Wu */ 6*6625ffb9SYong Wu #ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ 7*6625ffb9SYong Wu #define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ 8*6625ffb9SYong Wu 9*6625ffb9SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 10*6625ffb9SYong Wu 11*6625ffb9SYong Wu /* 12*6625ffb9SYong Wu * MM IOMMU supports 16GB dma address. We separate it to four ranges: 13*6625ffb9SYong Wu * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 14*6625ffb9SYong Wu * locate in anyone region. BUT: 15*6625ffb9SYong Wu * a) Make sure all the ports inside a larb are in one range. 16*6625ffb9SYong Wu * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 17*6625ffb9SYong Wu * 18*6625ffb9SYong Wu * This is the suggested mapping in this SoC: 19*6625ffb9SYong Wu * 20*6625ffb9SYong Wu * modules dma-address-region larbs-ports 21*6625ffb9SYong Wu * disp 0 ~ 4G larb0/1/2/3 22*6625ffb9SYong Wu * vcodec 4G ~ 8G larb19/20/21/22/23/24 23*6625ffb9SYong Wu * cam/mdp 8G ~ 12G the other larbs. 24*6625ffb9SYong Wu * N/A 12G ~ 16G 25*6625ffb9SYong Wu * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1 26*6625ffb9SYong Wu * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3 27*6625ffb9SYong Wu * 28*6625ffb9SYong Wu * This SoC have two IOMMU HWs, this is the detailed connected information: 29*6625ffb9SYong Wu * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28 30*6625ffb9SYong Wu * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27 31*6625ffb9SYong Wu */ 32*6625ffb9SYong Wu 33*6625ffb9SYong Wu /* MM IOMMU ports */ 34*6625ffb9SYong Wu /* larb0 */ 35*6625ffb9SYong Wu #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0) 36*6625ffb9SYong Wu #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1) 37*6625ffb9SYong Wu #define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2) 38*6625ffb9SYong Wu #define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3) 39*6625ffb9SYong Wu #define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4) 40*6625ffb9SYong Wu #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) 41*6625ffb9SYong Wu 42*6625ffb9SYong Wu /* larb1 */ 43*6625ffb9SYong Wu #define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0) 44*6625ffb9SYong Wu #define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1) 45*6625ffb9SYong Wu #define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2) 46*6625ffb9SYong Wu #define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3) 47*6625ffb9SYong Wu #define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4) 48*6625ffb9SYong Wu #define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5) 49*6625ffb9SYong Wu 50*6625ffb9SYong Wu /* larb2 */ 51*6625ffb9SYong Wu #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) 52*6625ffb9SYong Wu #define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1) 53*6625ffb9SYong Wu #define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2) 54*6625ffb9SYong Wu #define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3) 55*6625ffb9SYong Wu #define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4) 56*6625ffb9SYong Wu 57*6625ffb9SYong Wu /* larb3 */ 58*6625ffb9SYong Wu #define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0) 59*6625ffb9SYong Wu #define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1) 60*6625ffb9SYong Wu #define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2) 61*6625ffb9SYong Wu #define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3) 62*6625ffb9SYong Wu #define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4) 63*6625ffb9SYong Wu #define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5) 64*6625ffb9SYong Wu #define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6) 65*6625ffb9SYong Wu 66*6625ffb9SYong Wu /* larb4 */ 67*6625ffb9SYong Wu #define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0) 68*6625ffb9SYong Wu #define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1) 69*6625ffb9SYong Wu #define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2) 70*6625ffb9SYong Wu #define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3) 71*6625ffb9SYong Wu #define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4) 72*6625ffb9SYong Wu 73*6625ffb9SYong Wu /* larb5 */ 74*6625ffb9SYong Wu #define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0) 75*6625ffb9SYong Wu #define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1) 76*6625ffb9SYong Wu #define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2) 77*6625ffb9SYong Wu #define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3) 78*6625ffb9SYong Wu #define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4) 79*6625ffb9SYong Wu #define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5) 80*6625ffb9SYong Wu #define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6) 81*6625ffb9SYong Wu #define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7) 82*6625ffb9SYong Wu 83*6625ffb9SYong Wu /* larb6 */ 84*6625ffb9SYong Wu #define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0) 85*6625ffb9SYong Wu #define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1) 86*6625ffb9SYong Wu #define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2) 87*6625ffb9SYong Wu #define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3) 88*6625ffb9SYong Wu 89*6625ffb9SYong Wu /* larb7 */ 90*6625ffb9SYong Wu #define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0) 91*6625ffb9SYong Wu #define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1) 92*6625ffb9SYong Wu #define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2) 93*6625ffb9SYong Wu 94*6625ffb9SYong Wu /* larb8 */ 95*6625ffb9SYong Wu #define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0) 96*6625ffb9SYong Wu #define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1) 97*6625ffb9SYong Wu #define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2) 98*6625ffb9SYong Wu 99*6625ffb9SYong Wu /* larb9 */ 100*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0) 101*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1) 102*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2) 103*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3) 104*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4) 105*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5) 106*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6) 107*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7) 108*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8) 109*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9) 110*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10) 111*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11) 112*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12) 113*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13) 114*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14) 115*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15) 116*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16) 117*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17) 118*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18) 119*6625ffb9SYong Wu #define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19) 120*6625ffb9SYong Wu 121*6625ffb9SYong Wu /* larb10 */ 122*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0) 123*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1) 124*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2) 125*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3) 126*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4) 127*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5) 128*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6) 129*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7) 130*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8) 131*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9) 132*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10) 133*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11) 134*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12) 135*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13) 136*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14) 137*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15) 138*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16) 139*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17) 140*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18) 141*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19) 142*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20) 143*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21) 144*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22) 145*6625ffb9SYong Wu #define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23) 146*6625ffb9SYong Wu 147*6625ffb9SYong Wu /* larb11 */ 148*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0) 149*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1) 150*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2) 151*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3) 152*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4) 153*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5) 154*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6) 155*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7) 156*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8) 157*6625ffb9SYong Wu #define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9) 158*6625ffb9SYong Wu 159*6625ffb9SYong Wu /* larb12 */ 160*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0) 161*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1) 162*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2) 163*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3) 164*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4) 165*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5) 166*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6) 167*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7) 168*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8) 169*6625ffb9SYong Wu #define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9) 170*6625ffb9SYong Wu 171*6625ffb9SYong Wu /* larb13 */ 172*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0) 173*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1) 174*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2) 175*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3) 176*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4) 177*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5) 178*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6) 179*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7) 180*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8) 181*6625ffb9SYong Wu #define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9) 182*6625ffb9SYong Wu 183*6625ffb9SYong Wu /* larb14 */ 184*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0) 185*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1) 186*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2) 187*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3) 188*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4) 189*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5) 190*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6) 191*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7) 192*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8) 193*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9) 194*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10) 195*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11) 196*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12) 197*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13) 198*6625ffb9SYong Wu #define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14) 199*6625ffb9SYong Wu 200*6625ffb9SYong Wu /* larb15: null */ 201*6625ffb9SYong Wu 202*6625ffb9SYong Wu /* larb16 */ 203*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0) 204*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1) 205*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2) 206*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3) 207*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4) 208*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5) 209*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6) 210*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7) 211*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8) 212*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9) 213*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10) 214*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11) 215*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12) 216*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13) 217*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14) 218*6625ffb9SYong Wu #define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15) 219*6625ffb9SYong Wu 220*6625ffb9SYong Wu /* larb17 */ 221*6625ffb9SYong Wu #define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0) 222*6625ffb9SYong Wu #define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1) 223*6625ffb9SYong Wu #define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2) 224*6625ffb9SYong Wu #define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3) 225*6625ffb9SYong Wu #define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4) 226*6625ffb9SYong Wu #define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5) 227*6625ffb9SYong Wu #define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6) 228*6625ffb9SYong Wu 229*6625ffb9SYong Wu /* larb18 */ 230*6625ffb9SYong Wu #define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0) 231*6625ffb9SYong Wu #define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1) 232*6625ffb9SYong Wu #define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2) 233*6625ffb9SYong Wu #define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3) 234*6625ffb9SYong Wu 235*6625ffb9SYong Wu /* larb19 */ 236*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0) 237*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1) 238*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2) 239*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3) 240*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4) 241*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5) 242*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6) 243*6625ffb9SYong Wu #define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7) 244*6625ffb9SYong Wu #define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8) 245*6625ffb9SYong Wu #define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9) 246*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10) 247*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11) 248*6625ffb9SYong Wu #define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12) 249*6625ffb9SYong Wu #define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13) 250*6625ffb9SYong Wu #define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14) 251*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15) 252*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16) 253*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17) 254*6625ffb9SYong Wu #define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18) 255*6625ffb9SYong Wu #define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19) 256*6625ffb9SYong Wu #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20) 257*6625ffb9SYong Wu #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21) 258*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22) 259*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23) 260*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24) 261*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25) 262*6625ffb9SYong Wu #define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26) 263*6625ffb9SYong Wu 264*6625ffb9SYong Wu /* larb20 */ 265*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0) 266*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1) 267*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2) 268*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3) 269*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4) 270*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5) 271*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6) 272*6625ffb9SYong Wu #define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7) 273*6625ffb9SYong Wu #define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8) 274*6625ffb9SYong Wu #define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9) 275*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10) 276*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11) 277*6625ffb9SYong Wu #define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12) 278*6625ffb9SYong Wu #define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13) 279*6625ffb9SYong Wu #define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14) 280*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15) 281*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16) 282*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17) 283*6625ffb9SYong Wu #define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18) 284*6625ffb9SYong Wu #define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19) 285*6625ffb9SYong Wu #define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20) 286*6625ffb9SYong Wu #define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21) 287*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22) 288*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23) 289*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24) 290*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25) 291*6625ffb9SYong Wu #define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26) 292*6625ffb9SYong Wu 293*6625ffb9SYong Wu /* larb21 */ 294*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0) 295*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1) 296*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2) 297*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3) 298*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4) 299*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5) 300*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6) 301*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7) 302*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8) 303*6625ffb9SYong Wu #define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9) 304*6625ffb9SYong Wu 305*6625ffb9SYong Wu /* larb22 */ 306*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0) 307*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1) 308*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2) 309*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3) 310*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4) 311*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5) 312*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6) 313*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7) 314*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8) 315*6625ffb9SYong Wu #define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9) 316*6625ffb9SYong Wu 317*6625ffb9SYong Wu /* larb23 */ 318*6625ffb9SYong Wu #define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0) 319*6625ffb9SYong Wu #define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1) 320*6625ffb9SYong Wu 321*6625ffb9SYong Wu /* larb24 */ 322*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0) 323*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1) 324*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2) 325*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3) 326*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4) 327*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5) 328*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6) 329*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7) 330*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8) 331*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9) 332*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10) 333*6625ffb9SYong Wu #define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11) 334*6625ffb9SYong Wu 335*6625ffb9SYong Wu /* larb25 */ 336*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0) 337*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1) 338*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2) 339*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3) 340*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4) 341*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5) 342*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6) 343*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7) 344*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8) 345*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9) 346*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10) 347*6625ffb9SYong Wu #define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11) 348*6625ffb9SYong Wu 349*6625ffb9SYong Wu /* larb26 */ 350*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0) 351*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1) 352*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2) 353*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3) 354*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4) 355*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5) 356*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6) 357*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7) 358*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8) 359*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9) 360*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10) 361*6625ffb9SYong Wu #define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11) 362*6625ffb9SYong Wu 363*6625ffb9SYong Wu /* larb27 */ 364*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0) 365*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1) 366*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2) 367*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3) 368*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4) 369*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5) 370*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6) 371*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7) 372*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8) 373*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9) 374*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10) 375*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11) 376*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12) 377*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13) 378*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14) 379*6625ffb9SYong Wu #define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15) 380*6625ffb9SYong Wu 381*6625ffb9SYong Wu /* larb28 */ 382*6625ffb9SYong Wu #define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0) 383*6625ffb9SYong Wu #define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1) 384*6625ffb9SYong Wu #define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2) 385*6625ffb9SYong Wu #define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3) 386*6625ffb9SYong Wu #define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4) 387*6625ffb9SYong Wu #define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5) 388*6625ffb9SYong Wu #define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6) 389*6625ffb9SYong Wu 390*6625ffb9SYong Wu #endif 391