1fb6e2ceeSYong Wu /* 2fb6e2ceeSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 3fb6e2ceeSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 4fb6e2ceeSYong Wu * 5fb6e2ceeSYong Wu * This program is free software; you can redistribute it and/or modify 6fb6e2ceeSYong Wu * it under the terms of the GNU General Public License version 2 as 7fb6e2ceeSYong Wu * published by the Free Software Foundation. 8fb6e2ceeSYong Wu * 9fb6e2ceeSYong Wu * This program is distributed in the hope that it will be useful, 10fb6e2ceeSYong Wu * but WITHOUT ANY WARRANTY; without even the implied warranty of 11fb6e2ceeSYong Wu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12fb6e2ceeSYong Wu * GNU General Public License for more details. 13fb6e2ceeSYong Wu */ 14fb6e2ceeSYong Wu #ifndef __DTS_IOMMU_PORT_MT8173_H 15fb6e2ceeSYong Wu #define __DTS_IOMMU_PORT_MT8173_H 16fb6e2ceeSYong Wu 17fb6e2ceeSYong Wu #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) 18fb6e2ceeSYong Wu /* Local arbiter ID */ 19fb6e2ceeSYong Wu #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x7) 20fb6e2ceeSYong Wu /* PortID within the local arbiter */ 21fb6e2ceeSYong Wu #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) 22fb6e2ceeSYong Wu 23fb6e2ceeSYong Wu #define M4U_LARB0_ID 0 24fb6e2ceeSYong Wu #define M4U_LARB1_ID 1 25fb6e2ceeSYong Wu #define M4U_LARB2_ID 2 26fb6e2ceeSYong Wu #define M4U_LARB3_ID 3 27fb6e2ceeSYong Wu #define M4U_LARB4_ID 4 28fb6e2ceeSYong Wu #define M4U_LARB5_ID 5 29fb6e2ceeSYong Wu 30fb6e2ceeSYong Wu /* larb0 */ 31fb6e2ceeSYong Wu #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 32fb6e2ceeSYong Wu #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 33fb6e2ceeSYong Wu #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 34fb6e2ceeSYong Wu #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 35fb6e2ceeSYong Wu #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 36fb6e2ceeSYong Wu #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 37fb6e2ceeSYong Wu #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 38fb6e2ceeSYong Wu #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 39fb6e2ceeSYong Wu 40fb6e2ceeSYong Wu /* larb1 */ 41fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 42fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 43fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 44fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 45fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 46fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 47fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 48fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 49fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 50fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 51fb6e2ceeSYong Wu 52fb6e2ceeSYong Wu /* larb2 */ 53fb6e2ceeSYong Wu #define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) 54fb6e2ceeSYong Wu #define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) 55fb6e2ceeSYong Wu #define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) 56fb6e2ceeSYong Wu #define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) 57fb6e2ceeSYong Wu #define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) 58fb6e2ceeSYong Wu #define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5) 59fb6e2ceeSYong Wu #define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) 60fb6e2ceeSYong Wu #define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) 61fb6e2ceeSYong Wu #define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) 62fb6e2ceeSYong Wu #define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) 63fb6e2ceeSYong Wu #define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) 64fb6e2ceeSYong Wu #define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) 65fb6e2ceeSYong Wu #define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) 66fb6e2ceeSYong Wu #define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) 67fb6e2ceeSYong Wu #define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) 68fb6e2ceeSYong Wu #define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) 69fb6e2ceeSYong Wu #define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) 70fb6e2ceeSYong Wu #define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) 71fb6e2ceeSYong Wu #define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18) 72fb6e2ceeSYong Wu #define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19) 73fb6e2ceeSYong Wu #define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20) 74fb6e2ceeSYong Wu 75fb6e2ceeSYong Wu /* larb3 */ 76fb6e2ceeSYong Wu #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 77fb6e2ceeSYong Wu #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 78fb6e2ceeSYong Wu #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 79fb6e2ceeSYong Wu #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 80fb6e2ceeSYong Wu #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 81fb6e2ceeSYong Wu #define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) 82fb6e2ceeSYong Wu #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) 83fb6e2ceeSYong Wu #define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) 84fb6e2ceeSYong Wu #define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) 85fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) 86fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) 87fb6e2ceeSYong Wu #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) 88fb6e2ceeSYong Wu #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) 89fb6e2ceeSYong Wu #define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13) 90fb6e2ceeSYong Wu #define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14) 91fb6e2ceeSYong Wu 92fb6e2ceeSYong Wu /* larb4 */ 93fb6e2ceeSYong Wu #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 94fb6e2ceeSYong Wu #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 95fb6e2ceeSYong Wu #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2) 96fb6e2ceeSYong Wu #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3) 97fb6e2ceeSYong Wu #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4) 98fb6e2ceeSYong Wu #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5) 99fb6e2ceeSYong Wu 100fb6e2ceeSYong Wu /* larb5 */ 101fb6e2ceeSYong Wu #define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0) 102fb6e2ceeSYong Wu #define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1) 103fb6e2ceeSYong Wu #define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2) 104fb6e2ceeSYong Wu #define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3) 105fb6e2ceeSYong Wu #define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4) 106fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5) 107fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6) 108fb6e2ceeSYong Wu #define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7) 109fb6e2ceeSYong Wu #define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8) 110fb6e2ceeSYong Wu 111fb6e2ceeSYong Wu #endif 112