11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2fb6e2ceeSYong Wu /* 3fb6e2ceeSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4fb6e2ceeSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5fb6e2ceeSYong Wu */ 6*ddd3e349SYong Wu #ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ 7*ddd3e349SYong Wu #define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ 8fb6e2ceeSYong Wu 95cf482f2SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 10fb6e2ceeSYong Wu 11fb6e2ceeSYong Wu #define M4U_LARB0_ID 0 12fb6e2ceeSYong Wu #define M4U_LARB1_ID 1 13fb6e2ceeSYong Wu #define M4U_LARB2_ID 2 14fb6e2ceeSYong Wu #define M4U_LARB3_ID 3 15fb6e2ceeSYong Wu #define M4U_LARB4_ID 4 16fb6e2ceeSYong Wu #define M4U_LARB5_ID 5 17fb6e2ceeSYong Wu 18fb6e2ceeSYong Wu /* larb0 */ 19fb6e2ceeSYong Wu #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 20fb6e2ceeSYong Wu #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 21fb6e2ceeSYong Wu #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 22fb6e2ceeSYong Wu #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 23fb6e2ceeSYong Wu #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 24fb6e2ceeSYong Wu #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 25fb6e2ceeSYong Wu #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 26fb6e2ceeSYong Wu #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 27fb6e2ceeSYong Wu 28fb6e2ceeSYong Wu /* larb1 */ 29fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 30fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 31fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 32fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 33fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 34fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 35fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 36fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 37fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 38fb6e2ceeSYong Wu #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 39fb6e2ceeSYong Wu 40fb6e2ceeSYong Wu /* larb2 */ 41fb6e2ceeSYong Wu #define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) 42fb6e2ceeSYong Wu #define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) 43fb6e2ceeSYong Wu #define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) 44fb6e2ceeSYong Wu #define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) 45fb6e2ceeSYong Wu #define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) 46fb6e2ceeSYong Wu #define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5) 47fb6e2ceeSYong Wu #define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) 48fb6e2ceeSYong Wu #define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) 49fb6e2ceeSYong Wu #define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) 50fb6e2ceeSYong Wu #define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) 51fb6e2ceeSYong Wu #define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) 52fb6e2ceeSYong Wu #define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) 53fb6e2ceeSYong Wu #define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) 54fb6e2ceeSYong Wu #define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) 55fb6e2ceeSYong Wu #define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) 56fb6e2ceeSYong Wu #define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) 57fb6e2ceeSYong Wu #define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) 58fb6e2ceeSYong Wu #define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) 59fb6e2ceeSYong Wu #define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18) 60fb6e2ceeSYong Wu #define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19) 61fb6e2ceeSYong Wu #define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20) 62fb6e2ceeSYong Wu 63fb6e2ceeSYong Wu /* larb3 */ 64fb6e2ceeSYong Wu #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 65fb6e2ceeSYong Wu #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 66fb6e2ceeSYong Wu #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 67fb6e2ceeSYong Wu #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 68fb6e2ceeSYong Wu #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 69fb6e2ceeSYong Wu #define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) 70fb6e2ceeSYong Wu #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) 71fb6e2ceeSYong Wu #define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) 72fb6e2ceeSYong Wu #define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) 73fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) 74fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) 75fb6e2ceeSYong Wu #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) 76fb6e2ceeSYong Wu #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) 77fb6e2ceeSYong Wu #define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13) 78fb6e2ceeSYong Wu #define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14) 79fb6e2ceeSYong Wu 80fb6e2ceeSYong Wu /* larb4 */ 81fb6e2ceeSYong Wu #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 82fb6e2ceeSYong Wu #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 83fb6e2ceeSYong Wu #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2) 84fb6e2ceeSYong Wu #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3) 85fb6e2ceeSYong Wu #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4) 86fb6e2ceeSYong Wu #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5) 87fb6e2ceeSYong Wu 88fb6e2ceeSYong Wu /* larb5 */ 89fb6e2ceeSYong Wu #define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0) 90fb6e2ceeSYong Wu #define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1) 91fb6e2ceeSYong Wu #define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2) 92fb6e2ceeSYong Wu #define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3) 93fb6e2ceeSYong Wu #define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4) 94fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5) 95fb6e2ceeSYong Wu #define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6) 96fb6e2ceeSYong Wu #define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7) 97fb6e2ceeSYong Wu #define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8) 98fb6e2ceeSYong Wu 99fb6e2ceeSYong Wu #endif 100