1f7f842ccSFabien Parent /* SPDX-License-Identifier: GPL-2.0 */ 2f7f842ccSFabien Parent /* 3f7f842ccSFabien Parent * Copyright (c) 2020 MediaTek Inc. 4f7f842ccSFabien Parent * Copyright (c) 2020 BayLibre, SAS 5f7f842ccSFabien Parent * Author: Honghui Zhang <honghui.zhang@mediatek.com> 6f7f842ccSFabien Parent * Author: Fabien Parent <fparent@baylibre.com> 7f7f842ccSFabien Parent */ 8*ddd3e349SYong Wu #ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ 9*ddd3e349SYong Wu #define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ 10f7f842ccSFabien Parent 115cf482f2SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 12f7f842ccSFabien Parent 13f7f842ccSFabien Parent #define M4U_LARB0_ID 0 14f7f842ccSFabien Parent #define M4U_LARB1_ID 1 15f7f842ccSFabien Parent #define M4U_LARB2_ID 2 16f7f842ccSFabien Parent 17f7f842ccSFabien Parent /* larb0 */ 18f7f842ccSFabien Parent #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 19f7f842ccSFabien Parent #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 20f7f842ccSFabien Parent #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 21f7f842ccSFabien Parent #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3) 22f7f842ccSFabien Parent #define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) 23f7f842ccSFabien Parent #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) 24f7f842ccSFabien Parent #define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) 25f7f842ccSFabien Parent #define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) 26f7f842ccSFabien Parent 27f7f842ccSFabien Parent /* larb1*/ 28f7f842ccSFabien Parent #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) 29f7f842ccSFabien Parent #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) 30f7f842ccSFabien Parent #define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) 31f7f842ccSFabien Parent #define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) 32f7f842ccSFabien Parent #define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) 33f7f842ccSFabien Parent #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) 34f7f842ccSFabien Parent #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6) 35f7f842ccSFabien Parent #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) 36f7f842ccSFabien Parent #define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) 37f7f842ccSFabien Parent #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) 38f7f842ccSFabien Parent #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) 39f7f842ccSFabien Parent #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) 40f7f842ccSFabien Parent #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) 41f7f842ccSFabien Parent 42f7f842ccSFabien Parent /* larb2*/ 43f7f842ccSFabien Parent #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) 44f7f842ccSFabien Parent #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) 45f7f842ccSFabien Parent #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) 46f7f842ccSFabien Parent #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) 47f7f842ccSFabien Parent #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) 48f7f842ccSFabien Parent #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) 49f7f842ccSFabien Parent #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) 50f7f842ccSFabien Parent 51f7f842ccSFabien Parent #endif 52