1*d5cda142SChengci.Xu /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*d5cda142SChengci.Xu /* 3*d5cda142SChengci.Xu * Copyright (c) 2022 MediaTek Inc. 4*d5cda142SChengci.Xu * Author: Chengci Xu <chengci.xu@mediatek.com> 5*d5cda142SChengci.Xu */ 6*d5cda142SChengci.Xu #ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_ 7*d5cda142SChengci.Xu #define _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_ 8*d5cda142SChengci.Xu 9*d5cda142SChengci.Xu #include <dt-bindings/memory/mtk-memory-port.h> 10*d5cda142SChengci.Xu 11*d5cda142SChengci.Xu /* 12*d5cda142SChengci.Xu * MM IOMMU larbs: 13*d5cda142SChengci.Xu * From below, for example larb11 has larb11a/larb11b/larb11c, 14*d5cda142SChengci.Xu * the index of larb is not in order. So we reindexed these larbs from a 15*d5cda142SChengci.Xu * software view. 16*d5cda142SChengci.Xu */ 17*d5cda142SChengci.Xu #define SMI_L0_ID 0 18*d5cda142SChengci.Xu #define SMI_L1_ID 1 19*d5cda142SChengci.Xu #define SMI_L2_ID 2 20*d5cda142SChengci.Xu #define SMI_L3_ID 3 21*d5cda142SChengci.Xu #define SMI_L4_ID 4 22*d5cda142SChengci.Xu #define SMI_L5_ID 5 23*d5cda142SChengci.Xu #define SMI_L6_ID 6 24*d5cda142SChengci.Xu #define SMI_L7_ID 7 25*d5cda142SChengci.Xu #define SMI_L9_ID 8 26*d5cda142SChengci.Xu #define SMI_L10_ID 9 27*d5cda142SChengci.Xu #define SMI_L11A_ID 10 28*d5cda142SChengci.Xu #define SMI_L11B_ID 11 29*d5cda142SChengci.Xu #define SMI_L11C_ID 12 30*d5cda142SChengci.Xu #define SMI_L12_ID 13 31*d5cda142SChengci.Xu #define SMI_L13_ID 14 32*d5cda142SChengci.Xu #define SMI_L14_ID 15 33*d5cda142SChengci.Xu #define SMI_L15_ID 16 34*d5cda142SChengci.Xu #define SMI_L16A_ID 17 35*d5cda142SChengci.Xu #define SMI_L16B_ID 18 36*d5cda142SChengci.Xu #define SMI_L17A_ID 19 37*d5cda142SChengci.Xu #define SMI_L17B_ID 20 38*d5cda142SChengci.Xu #define SMI_L19_ID 21 39*d5cda142SChengci.Xu #define SMI_L21_ID 22 40*d5cda142SChengci.Xu #define SMI_L23_ID 23 41*d5cda142SChengci.Xu #define SMI_L27_ID 24 42*d5cda142SChengci.Xu #define SMI_L28_ID 25 43*d5cda142SChengci.Xu 44*d5cda142SChengci.Xu /* 45*d5cda142SChengci.Xu * MM IOMMU supports 16GB dma address. We separate it to four ranges: 46*d5cda142SChengci.Xu * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 47*d5cda142SChengci.Xu * locate in anyone region. BUT: 48*d5cda142SChengci.Xu * a) Make sure all the ports inside a larb are in one range. 49*d5cda142SChengci.Xu * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 50*d5cda142SChengci.Xu * 51*d5cda142SChengci.Xu * This is the suggested mapping in this SoC: 52*d5cda142SChengci.Xu * 53*d5cda142SChengci.Xu * modules dma-address-region larbs-ports 54*d5cda142SChengci.Xu * disp 0 ~ 4G larb0/1/2/3 55*d5cda142SChengci.Xu * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23 56*d5cda142SChengci.Xu * cam/mdp 8G ~ 12G the other larbs. 57*d5cda142SChengci.Xu * N/A 12G ~ 16G 58*d5cda142SChengci.Xu * CCU0 0x24000_0000 ~ 0x243ff_ffff larb27(24): port 0/1 59*d5cda142SChengci.Xu * CCU1 0x24400_0000 ~ 0x247ff_ffff larb27(24): port 2/3 60*d5cda142SChengci.Xu * 61*d5cda142SChengci.Xu * This SoC have two MM IOMMU HWs, this is the connected information: 62*d5cda142SChengci.Xu * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21 63*d5cda142SChengci.Xu * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27 64*d5cda142SChengci.Xu * 65*d5cda142SChengci.Xu * [1]: This is larb19, but the index is 21 from the SW view. 66*d5cda142SChengci.Xu */ 67*d5cda142SChengci.Xu 68*d5cda142SChengci.Xu /* MM IOMMU ports */ 69*d5cda142SChengci.Xu /* LARB 0 -- VDO-0 */ 70*d5cda142SChengci.Xu #define M4U_PORT_L0_DISP_RDMA1 MTK_M4U_ID(SMI_L0_ID, 0) 71*d5cda142SChengci.Xu #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 1) 72*d5cda142SChengci.Xu #define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(SMI_L0_ID, 2) 73*d5cda142SChengci.Xu #define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(SMI_L0_ID, 3) 74*d5cda142SChengci.Xu #define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(SMI_L0_ID, 4) 75*d5cda142SChengci.Xu #define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(SMI_L0_ID, 5) 76*d5cda142SChengci.Xu #define M4U_PORT_L0_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 6) 77*d5cda142SChengci.Xu 78*d5cda142SChengci.Xu /* LARB 1 -- VD0-0 */ 79*d5cda142SChengci.Xu #define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(SMI_L1_ID, 0) 80*d5cda142SChengci.Xu #define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 1) 81*d5cda142SChengci.Xu #define M4U_PORT_L1_DISP_OVL1_RDMA0 MTK_M4U_ID(SMI_L1_ID, 2) 82*d5cda142SChengci.Xu #define M4U_PORT_L1_DISP_OVL1_RDMA1 MTK_M4U_ID(SMI_L1_ID, 3) 83*d5cda142SChengci.Xu #define M4U_PORT_L1_DISP_OVL1_HDR MTK_M4U_ID(SMI_L1_ID, 4) 84*d5cda142SChengci.Xu #define M4U_PORT_L1_DISP_WROT0 MTK_M4U_ID(SMI_L1_ID, 5) 85*d5cda142SChengci.Xu #define M4U_PORT_L1_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 6) 86*d5cda142SChengci.Xu 87*d5cda142SChengci.Xu /* LARB 2 -- VDO-1 */ 88*d5cda142SChengci.Xu #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0) 89*d5cda142SChengci.Xu #define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 1) 90*d5cda142SChengci.Xu #define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(SMI_L2_ID, 2) 91*d5cda142SChengci.Xu #define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(SMI_L2_ID, 3) 92*d5cda142SChengci.Xu #define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(SMI_L2_ID, 4) 93*d5cda142SChengci.Xu 94*d5cda142SChengci.Xu /* LARB 3 -- VDO-1 */ 95*d5cda142SChengci.Xu #define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(SMI_L3_ID, 0) 96*d5cda142SChengci.Xu #define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(SMI_L3_ID, 1) 97*d5cda142SChengci.Xu #define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(SMI_L3_ID, 2) 98*d5cda142SChengci.Xu #define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(SMI_L3_ID, 3) 99*d5cda142SChengci.Xu #define M4U_PORT_L3_HDR_DS_SMI MTK_M4U_ID(SMI_L3_ID, 4) 100*d5cda142SChengci.Xu #define M4U_PORT_L3_HDR_ADL_SMI MTK_M4U_ID(SMI_L3_ID, 5) 101*d5cda142SChengci.Xu #define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(SMI_L3_ID, 6) 102*d5cda142SChengci.Xu 103*d5cda142SChengci.Xu /* LARB 4 -- VPP-0 */ 104*d5cda142SChengci.Xu #define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(SMI_L4_ID, 0) 105*d5cda142SChengci.Xu #define M4U_PORT_L4_MDP_FG MTK_M4U_ID(SMI_L4_ID, 1) 106*d5cda142SChengci.Xu #define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(SMI_L4_ID, 2) 107*d5cda142SChengci.Xu #define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(SMI_L4_ID, 3) 108*d5cda142SChengci.Xu #define M4U_PORT_L4_FAKE_ENG MTK_M4U_ID(SMI_L4_ID, 4) 109*d5cda142SChengci.Xu #define M4U_PORT_L4_DISP_RDMA MTK_M4U_ID(SMI_L4_ID, 5) 110*d5cda142SChengci.Xu #define M4U_PORT_L4_DISP_WDMA MTK_M4U_ID(SMI_L4_ID, 6) 111*d5cda142SChengci.Xu 112*d5cda142SChengci.Xu /* LARB 5 -- VPP-1 */ 113*d5cda142SChengci.Xu #define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 0) 114*d5cda142SChengci.Xu #define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(SMI_L5_ID, 1) 115*d5cda142SChengci.Xu #define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(SMI_L5_ID, 2) 116*d5cda142SChengci.Xu #define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 3) 117*d5cda142SChengci.Xu #define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 4) 118*d5cda142SChengci.Xu #define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(SMI_L5_ID, 5) 119*d5cda142SChengci.Xu #define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 6) 120*d5cda142SChengci.Xu #define M4U_PORT_L5_LARB5_FAKE_ENG MTK_M4U_ID(SMI_L5_ID, 7) 121*d5cda142SChengci.Xu 122*d5cda142SChengci.Xu /* LARB 6 -- VPP-1 */ 123*d5cda142SChengci.Xu #define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(SMI_L6_ID, 0) 124*d5cda142SChengci.Xu #define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(SMI_L6_ID, 1) 125*d5cda142SChengci.Xu #define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(SMI_L6_ID, 2) 126*d5cda142SChengci.Xu #define M4U_PORT_L6_LARB6_FAKE_ENG MTK_M4U_ID(SMI_L6_ID, 3) 127*d5cda142SChengci.Xu 128*d5cda142SChengci.Xu /* LARB 7 -- WPE */ 129*d5cda142SChengci.Xu #define M4U_PORT_L7_WPE_RDMA_0 MTK_M4U_ID(SMI_L7_ID, 0) 130*d5cda142SChengci.Xu #define M4U_PORT_L7_WPE_RDMA_1 MTK_M4U_ID(SMI_L7_ID, 1) 131*d5cda142SChengci.Xu #define M4U_PORT_L7_WPE_WDMA_0 MTK_M4U_ID(SMI_L7_ID, 2) 132*d5cda142SChengci.Xu 133*d5cda142SChengci.Xu /* LARB 9 -- IMG-M */ 134*d5cda142SChengci.Xu #define M4U_PORT_L9_IMGI_T1_A MTK_M4U_ID(SMI_L9_ID, 0) 135*d5cda142SChengci.Xu #define M4U_PORT_L9_UFDI_T1_A MTK_M4U_ID(SMI_L9_ID, 1) 136*d5cda142SChengci.Xu #define M4U_PORT_L9_IMGBI_T1_A MTK_M4U_ID(SMI_L9_ID, 2) 137*d5cda142SChengci.Xu #define M4U_PORT_L9_IMGCI_T1_A MTK_M4U_ID(SMI_L9_ID, 3) 138*d5cda142SChengci.Xu #define M4U_PORT_L9_SMTI_T1_A MTK_M4U_ID(SMI_L9_ID, 4) 139*d5cda142SChengci.Xu #define M4U_PORT_L9_SMTI_T4_A MTK_M4U_ID(SMI_L9_ID, 5) 140*d5cda142SChengci.Xu #define M4U_PORT_L9_TNCSTI_T1_A MTK_M4U_ID(SMI_L9_ID, 6) 141*d5cda142SChengci.Xu #define M4U_PORT_L9_TNCSTI_T4_A MTK_M4U_ID(SMI_L9_ID, 7) 142*d5cda142SChengci.Xu #define M4U_PORT_L9_YUVO_T1_A MTK_M4U_ID(SMI_L9_ID, 8) 143*d5cda142SChengci.Xu #define M4U_PORT_L9_YUVBO_T1_A MTK_M4U_ID(SMI_L9_ID, 9) 144*d5cda142SChengci.Xu #define M4U_PORT_L9_YUVCO_T1_A MTK_M4U_ID(SMI_L9_ID, 10) 145*d5cda142SChengci.Xu #define M4U_PORT_L9_TIMGO_T1_A MTK_M4U_ID(SMI_L9_ID, 11) 146*d5cda142SChengci.Xu #define M4U_PORT_L9_YUVO_T2_A MTK_M4U_ID(SMI_L9_ID, 12) 147*d5cda142SChengci.Xu #define M4U_PORT_L9_YUVO_T5_A MTK_M4U_ID(SMI_L9_ID, 13) 148*d5cda142SChengci.Xu #define M4U_PORT_L9_IMGI_T1_B MTK_M4U_ID(SMI_L9_ID, 14) 149*d5cda142SChengci.Xu #define M4U_PORT_L9_IMGBI_T1_B MTK_M4U_ID(SMI_L9_ID, 15) 150*d5cda142SChengci.Xu #define M4U_PORT_L9_IMGCI_T1_B MTK_M4U_ID(SMI_L9_ID, 16) 151*d5cda142SChengci.Xu #define M4U_PORT_L9_SMTI_T4_B MTK_M4U_ID(SMI_L9_ID, 17) 152*d5cda142SChengci.Xu #define M4U_PORT_L9_TNCSO_T1_A MTK_M4U_ID(SMI_L9_ID, 18) 153*d5cda142SChengci.Xu #define M4U_PORT_L9_SMTO_T1_A MTK_M4U_ID(SMI_L9_ID, 19) 154*d5cda142SChengci.Xu #define M4U_PORT_L9_SMTO_T4_A MTK_M4U_ID(SMI_L9_ID, 20) 155*d5cda142SChengci.Xu #define M4U_PORT_L9_TNCSTO_T1_A MTK_M4U_ID(SMI_L9_ID, 21) 156*d5cda142SChengci.Xu #define M4U_PORT_L9_YUVO_T2_B MTK_M4U_ID(SMI_L9_ID, 22) 157*d5cda142SChengci.Xu #define M4U_PORT_L9_YUVO_T5_B MTK_M4U_ID(SMI_L9_ID, 23) 158*d5cda142SChengci.Xu #define M4U_PORT_L9_SMTO_T4_B MTK_M4U_ID(SMI_L9_ID, 24) 159*d5cda142SChengci.Xu 160*d5cda142SChengci.Xu /* LARB 10 -- IMG-D */ 161*d5cda142SChengci.Xu #define M4U_PORT_L10_IMGI_D1 MTK_M4U_ID(SMI_L10_ID, 0) 162*d5cda142SChengci.Xu #define M4U_PORT_L10_IMGBI_D1 MTK_M4U_ID(SMI_L10_ID, 1) 163*d5cda142SChengci.Xu #define M4U_PORT_L10_IMGCI_D1 MTK_M4U_ID(SMI_L10_ID, 2) 164*d5cda142SChengci.Xu #define M4U_PORT_L10_IMGDI_D1 MTK_M4U_ID(SMI_L10_ID, 3) 165*d5cda142SChengci.Xu #define M4U_PORT_L10_DEPI_D1 MTK_M4U_ID(SMI_L10_ID, 4) 166*d5cda142SChengci.Xu #define M4U_PORT_L10_DMGI_D1 MTK_M4U_ID(SMI_L10_ID, 5) 167*d5cda142SChengci.Xu #define M4U_PORT_L10_SMTI_D1 MTK_M4U_ID(SMI_L10_ID, 6) 168*d5cda142SChengci.Xu #define M4U_PORT_L10_RECI_D1 MTK_M4U_ID(SMI_L10_ID, 7) 169*d5cda142SChengci.Xu #define M4U_PORT_L10_RECI_D1_N MTK_M4U_ID(SMI_L10_ID, 8) 170*d5cda142SChengci.Xu #define M4U_PORT_L10_TNRWI_D1 MTK_M4U_ID(SMI_L10_ID, 9) 171*d5cda142SChengci.Xu #define M4U_PORT_L10_TNRCI_D1 MTK_M4U_ID(SMI_L10_ID, 10) 172*d5cda142SChengci.Xu #define M4U_PORT_L10_TNRCI_D1_N MTK_M4U_ID(SMI_L10_ID, 11) 173*d5cda142SChengci.Xu #define M4U_PORT_L10_IMG4O_D1 MTK_M4U_ID(SMI_L10_ID, 12) 174*d5cda142SChengci.Xu #define M4U_PORT_L10_IMG4BO_D1 MTK_M4U_ID(SMI_L10_ID, 13) 175*d5cda142SChengci.Xu #define M4U_PORT_L10_SMTI_D8 MTK_M4U_ID(SMI_L10_ID, 14) 176*d5cda142SChengci.Xu #define M4U_PORT_L10_SMTO_D1 MTK_M4U_ID(SMI_L10_ID, 15) 177*d5cda142SChengci.Xu #define M4U_PORT_L10_TNRMO_D1 MTK_M4U_ID(SMI_L10_ID, 16) 178*d5cda142SChengci.Xu #define M4U_PORT_L10_TNRMO_D1_N MTK_M4U_ID(SMI_L10_ID, 17) 179*d5cda142SChengci.Xu #define M4U_PORT_L10_SMTO_D8 MTK_M4U_ID(SMI_L10_ID, 18) 180*d5cda142SChengci.Xu #define M4U_PORT_L10_DBGO_D1 MTK_M4U_ID(SMI_L10_ID, 19) 181*d5cda142SChengci.Xu 182*d5cda142SChengci.Xu /* LARB 11A -- IMG-D */ 183*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_RDMA_0 MTK_M4U_ID(SMI_L11A_ID, 0) 184*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_RDMA_1 MTK_M4U_ID(SMI_L11A_ID, 1) 185*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 2) 186*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11A_ID, 3) 187*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_CQ0 MTK_M4U_ID(SMI_L11A_ID, 4) 188*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_CQ1 MTK_M4U_ID(SMI_L11A_ID, 5) 189*d5cda142SChengci.Xu #define M4U_PORT_L11A_PIMGI_P1 MTK_M4U_ID(SMI_L11A_ID, 6) 190*d5cda142SChengci.Xu #define M4U_PORT_L11A_PIMGBI_P1 MTK_M4U_ID(SMI_L11A_ID, 7) 191*d5cda142SChengci.Xu #define M4U_PORT_L11A_PIMGCI_P1 MTK_M4U_ID(SMI_L11A_ID, 8) 192*d5cda142SChengci.Xu #define M4U_PORT_L11A_IMGI_T1_C MTK_M4U_ID(SMI_L11A_ID, 9) 193*d5cda142SChengci.Xu #define M4U_PORT_L11A_IMGBI_T1_C MTK_M4U_ID(SMI_L11A_ID, 10) 194*d5cda142SChengci.Xu #define M4U_PORT_L11A_IMGCI_T1_C MTK_M4U_ID(SMI_L11A_ID, 11) 195*d5cda142SChengci.Xu #define M4U_PORT_L11A_SMTI_T1_C MTK_M4U_ID(SMI_L11A_ID, 12) 196*d5cda142SChengci.Xu #define M4U_PORT_L11A_SMTI_T4_C MTK_M4U_ID(SMI_L11A_ID, 13) 197*d5cda142SChengci.Xu #define M4U_PORT_L11A_SMTI_T6_C MTK_M4U_ID(SMI_L11A_ID, 14) 198*d5cda142SChengci.Xu #define M4U_PORT_L11A_YUVO_T1_C MTK_M4U_ID(SMI_L11A_ID, 15) 199*d5cda142SChengci.Xu #define M4U_PORT_L11A_YUVBO_T1_C MTK_M4U_ID(SMI_L11A_ID, 16) 200*d5cda142SChengci.Xu #define M4U_PORT_L11A_YUVCO_T1_C MTK_M4U_ID(SMI_L11A_ID, 17) 201*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_WDMA_0 MTK_M4U_ID(SMI_L11A_ID, 18) 202*d5cda142SChengci.Xu #define M4U_PORT_L11A_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 19) 203*d5cda142SChengci.Xu #define M4U_PORT_L11A_WROT_P1 MTK_M4U_ID(SMI_L11A_ID, 20) 204*d5cda142SChengci.Xu #define M4U_PORT_L11A_TCCSO_P1 MTK_M4U_ID(SMI_L11A_ID, 21) 205*d5cda142SChengci.Xu #define M4U_PORT_L11A_TCCSI_P1 MTK_M4U_ID(SMI_L11A_ID, 22) 206*d5cda142SChengci.Xu #define M4U_PORT_L11A_TIMGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 23) 207*d5cda142SChengci.Xu #define M4U_PORT_L11A_YUVO_T2_C MTK_M4U_ID(SMI_L11A_ID, 24) 208*d5cda142SChengci.Xu #define M4U_PORT_L11A_YUVO_T5_C MTK_M4U_ID(SMI_L11A_ID, 25) 209*d5cda142SChengci.Xu #define M4U_PORT_L11A_SMTO_T1_C MTK_M4U_ID(SMI_L11A_ID, 26) 210*d5cda142SChengci.Xu #define M4U_PORT_L11A_SMTO_T4_C MTK_M4U_ID(SMI_L11A_ID, 27) 211*d5cda142SChengci.Xu #define M4U_PORT_L11A_SMTO_T6_C MTK_M4U_ID(SMI_L11A_ID, 28) 212*d5cda142SChengci.Xu #define M4U_PORT_L11A_DBGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 29) 213*d5cda142SChengci.Xu 214*d5cda142SChengci.Xu /* LARB 11B -- IMG-D */ 215*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_RDMA_0 MTK_M4U_ID(SMI_L11B_ID, 0) 216*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_RDMA_1 MTK_M4U_ID(SMI_L11B_ID, 1) 217*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 2) 218*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11B_ID, 3) 219*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_CQ0 MTK_M4U_ID(SMI_L11B_ID, 4) 220*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_CQ1 MTK_M4U_ID(SMI_L11B_ID, 5) 221*d5cda142SChengci.Xu #define M4U_PORT_L11B_PIMGI_P1 MTK_M4U_ID(SMI_L11B_ID, 6) 222*d5cda142SChengci.Xu #define M4U_PORT_L11B_PIMGBI_P1 MTK_M4U_ID(SMI_L11B_ID, 7) 223*d5cda142SChengci.Xu #define M4U_PORT_L11B_PIMGCI_P1 MTK_M4U_ID(SMI_L11B_ID, 8) 224*d5cda142SChengci.Xu #define M4U_PORT_L11B_IMGI_T1_C MTK_M4U_ID(SMI_L11B_ID, 9) 225*d5cda142SChengci.Xu #define M4U_PORT_L11B_IMGBI_T1_C MTK_M4U_ID(SMI_L11B_ID, 10) 226*d5cda142SChengci.Xu #define M4U_PORT_L11B_IMGCI_T1_C MTK_M4U_ID(SMI_L11B_ID, 11) 227*d5cda142SChengci.Xu #define M4U_PORT_L11B_SMTI_T1_C MTK_M4U_ID(SMI_L11B_ID, 12) 228*d5cda142SChengci.Xu #define M4U_PORT_L11B_SMTI_T4_C MTK_M4U_ID(SMI_L11B_ID, 13) 229*d5cda142SChengci.Xu #define M4U_PORT_L11B_SMTI_T6_C MTK_M4U_ID(SMI_L11B_ID, 14) 230*d5cda142SChengci.Xu #define M4U_PORT_L11B_YUVO_T1_C MTK_M4U_ID(SMI_L11B_ID, 15) 231*d5cda142SChengci.Xu #define M4U_PORT_L11B_YUVBO_T1_C MTK_M4U_ID(SMI_L11B_ID, 16) 232*d5cda142SChengci.Xu #define M4U_PORT_L11B_YUVCO_T1_C MTK_M4U_ID(SMI_L11B_ID, 17) 233*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_WDMA_0 MTK_M4U_ID(SMI_L11B_ID, 18) 234*d5cda142SChengci.Xu #define M4U_PORT_L11B_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 19) 235*d5cda142SChengci.Xu #define M4U_PORT_L11B_WROT_P1 MTK_M4U_ID(SMI_L11B_ID, 20) 236*d5cda142SChengci.Xu #define M4U_PORT_L11B_TCCSO_P1 MTK_M4U_ID(SMI_L11B_ID, 21) 237*d5cda142SChengci.Xu #define M4U_PORT_L11B_TCCSI_P1 MTK_M4U_ID(SMI_L11B_ID, 22) 238*d5cda142SChengci.Xu #define M4U_PORT_L11B_TIMGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 23) 239*d5cda142SChengci.Xu #define M4U_PORT_L11B_YUVO_T2_C MTK_M4U_ID(SMI_L11B_ID, 24) 240*d5cda142SChengci.Xu #define M4U_PORT_L11B_YUVO_T5_C MTK_M4U_ID(SMI_L11B_ID, 25) 241*d5cda142SChengci.Xu #define M4U_PORT_L11B_SMTO_T1_C MTK_M4U_ID(SMI_L11B_ID, 26) 242*d5cda142SChengci.Xu #define M4U_PORT_L11B_SMTO_T4_C MTK_M4U_ID(SMI_L11B_ID, 27) 243*d5cda142SChengci.Xu #define M4U_PORT_L11B_SMTO_T6_C MTK_M4U_ID(SMI_L11B_ID, 28) 244*d5cda142SChengci.Xu #define M4U_PORT_L11B_DBGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 29) 245*d5cda142SChengci.Xu 246*d5cda142SChengci.Xu /* LARB 11C -- IMG-D */ 247*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_RDMA_0 MTK_M4U_ID(SMI_L11C_ID, 0) 248*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_RDMA_1 MTK_M4U_ID(SMI_L11C_ID, 1) 249*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 2) 250*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11C_ID, 3) 251*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_CQ0 MTK_M4U_ID(SMI_L11C_ID, 4) 252*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_CQ1 MTK_M4U_ID(SMI_L11C_ID, 5) 253*d5cda142SChengci.Xu #define M4U_PORT_L11C_PIMGI_P1 MTK_M4U_ID(SMI_L11C_ID, 6) 254*d5cda142SChengci.Xu #define M4U_PORT_L11C_PIMGBI_P1 MTK_M4U_ID(SMI_L11C_ID, 7) 255*d5cda142SChengci.Xu #define M4U_PORT_L11C_PIMGCI_P1 MTK_M4U_ID(SMI_L11C_ID, 8) 256*d5cda142SChengci.Xu #define M4U_PORT_L11C_IMGI_T1_C MTK_M4U_ID(SMI_L11C_ID, 9) 257*d5cda142SChengci.Xu #define M4U_PORT_L11C_IMGBI_T1_C MTK_M4U_ID(SMI_L11C_ID, 10) 258*d5cda142SChengci.Xu #define M4U_PORT_L11C_IMGCI_T1_C MTK_M4U_ID(SMI_L11C_ID, 11) 259*d5cda142SChengci.Xu #define M4U_PORT_L11C_SMTI_T1_C MTK_M4U_ID(SMI_L11C_ID, 12) 260*d5cda142SChengci.Xu #define M4U_PORT_L11C_SMTI_T4_C MTK_M4U_ID(SMI_L11C_ID, 13) 261*d5cda142SChengci.Xu #define M4U_PORT_L11C_SMTI_T6_C MTK_M4U_ID(SMI_L11C_ID, 14) 262*d5cda142SChengci.Xu #define M4U_PORT_L11C_YUVO_T1_C MTK_M4U_ID(SMI_L11C_ID, 15) 263*d5cda142SChengci.Xu #define M4U_PORT_L11C_YUVBO_T1_C MTK_M4U_ID(SMI_L11C_ID, 16) 264*d5cda142SChengci.Xu #define M4U_PORT_L11C_YUVCO_T1_C MTK_M4U_ID(SMI_L11C_ID, 17) 265*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_WDMA_0 MTK_M4U_ID(SMI_L11C_ID, 18) 266*d5cda142SChengci.Xu #define M4U_PORT_L11C_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 19) 267*d5cda142SChengci.Xu #define M4U_PORT_L11C_WROT_P1 MTK_M4U_ID(SMI_L11C_ID, 20) 268*d5cda142SChengci.Xu #define M4U_PORT_L11C_TCCSO_P1 MTK_M4U_ID(SMI_L11C_ID, 21) 269*d5cda142SChengci.Xu #define M4U_PORT_L11C_TCCSI_P1 MTK_M4U_ID(SMI_L11C_ID, 22) 270*d5cda142SChengci.Xu #define M4U_PORT_L11C_TIMGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 23) 271*d5cda142SChengci.Xu #define M4U_PORT_L11C_YUVO_T2_C MTK_M4U_ID(SMI_L11C_ID, 24) 272*d5cda142SChengci.Xu #define M4U_PORT_L11C_YUVO_T5_C MTK_M4U_ID(SMI_L11C_ID, 25) 273*d5cda142SChengci.Xu #define M4U_PORT_L11C_SMTO_T1_C MTK_M4U_ID(SMI_L11C_ID, 26) 274*d5cda142SChengci.Xu #define M4U_PORT_L11C_SMTO_T4_C MTK_M4U_ID(SMI_L11C_ID, 27) 275*d5cda142SChengci.Xu #define M4U_PORT_L11C_SMTO_T6_C MTK_M4U_ID(SMI_L11C_ID, 28) 276*d5cda142SChengci.Xu #define M4U_PORT_L11C_DBGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 29) 277*d5cda142SChengci.Xu 278*d5cda142SChengci.Xu /* LARB 12 -- IPE */ 279*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_RDA_0 MTK_M4U_ID(SMI_L12_ID, 0) 280*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_RDB_0 MTK_M4U_ID(SMI_L12_ID, 1) 281*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_WRA_0 MTK_M4U_ID(SMI_L12_ID, 2) 282*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_WRB_0 MTK_M4U_ID(SMI_L12_ID, 3) 283*d5cda142SChengci.Xu #define M4U_PORT_L12_ME_RDMA MTK_M4U_ID(SMI_L12_ID, 4) 284*d5cda142SChengci.Xu #define M4U_PORT_L12_ME_WDMA MTK_M4U_ID(SMI_L12_ID, 5) 285*d5cda142SChengci.Xu #define M4U_PORT_L12_DVS_RDMA MTK_M4U_ID(SMI_L12_ID, 6) 286*d5cda142SChengci.Xu #define M4U_PORT_L12_DVS_WDMA MTK_M4U_ID(SMI_L12_ID, 7) 287*d5cda142SChengci.Xu #define M4U_PORT_L12_DVP_RDMA MTK_M4U_ID(SMI_L12_ID, 8) 288*d5cda142SChengci.Xu #define M4U_PORT_L12_DVP_WDMA MTK_M4U_ID(SMI_L12_ID, 9) 289*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_2ND_RDA_0 MTK_M4U_ID(SMI_L12_ID, 10) 290*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_2ND_RDB_0 MTK_M4U_ID(SMI_L12_ID, 11) 291*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_2ND_WRA_0 MTK_M4U_ID(SMI_L12_ID, 12) 292*d5cda142SChengci.Xu #define M4U_PORT_L12_FDVT_2ND_WRB_0 MTK_M4U_ID(SMI_L12_ID, 13) 293*d5cda142SChengci.Xu #define M4U_PORT_L12_DHZEI_E1 MTK_M4U_ID(SMI_L12_ID, 14) 294*d5cda142SChengci.Xu #define M4U_PORT_L12_DHZEO_E1 MTK_M4U_ID(SMI_L12_ID, 15) 295*d5cda142SChengci.Xu 296*d5cda142SChengci.Xu /* LARB 13 -- CAM-1 */ 297*d5cda142SChengci.Xu #define M4U_PORT_L13_CAMSV_CQI_E1 MTK_M4U_ID(SMI_L13_ID, 0) 298*d5cda142SChengci.Xu #define M4U_PORT_L13_CAMSV_CQI_E2 MTK_M4U_ID(SMI_L13_ID, 1) 299*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 2) 300*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_C_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 3) 301*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 4) 302*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_C_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 5) 303*d5cda142SChengci.Xu #define M4U_PORT_L13_PDAI_A_0 MTK_M4U_ID(SMI_L13_ID, 6) 304*d5cda142SChengci.Xu #define M4U_PORT_L13_PDAI_A_1 MTK_M4U_ID(SMI_L13_ID, 7) 305*d5cda142SChengci.Xu #define M4U_PORT_L13_CAMSV_CQI_B_E1 MTK_M4U_ID(SMI_L13_ID, 8) 306*d5cda142SChengci.Xu #define M4U_PORT_L13_CAMSV_CQI_B_E2 MTK_M4U_ID(SMI_L13_ID, 9) 307*d5cda142SChengci.Xu #define M4U_PORT_L13_CAMSV_CQI_C_E1 MTK_M4U_ID(SMI_L13_ID, 10) 308*d5cda142SChengci.Xu #define M4U_PORT_L13_CAMSV_CQI_C_E2 MTK_M4U_ID(SMI_L13_ID, 11) 309*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_E_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 12) 310*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_E_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 13) 311*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_A_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 14) 312*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_C_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 15) 313*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_A_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 16) 314*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_C_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 17) 315*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_E_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 18) 316*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_E_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 19) 317*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_G_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 20) 318*d5cda142SChengci.Xu #define M4U_PORT_L13_GCAMSV_G_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 21) 319*d5cda142SChengci.Xu #define M4U_PORT_L13_PDAO_A MTK_M4U_ID(SMI_L13_ID, 22) 320*d5cda142SChengci.Xu #define M4U_PORT_L13_PDAO_C MTK_M4U_ID(SMI_L13_ID, 23) 321*d5cda142SChengci.Xu 322*d5cda142SChengci.Xu /* LARB 14 -- CAM-1 */ 323*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 0) 324*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 1) 325*d5cda142SChengci.Xu #define M4U_PORT_L14_SCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 2) 326*d5cda142SChengci.Xu #define M4U_PORT_L14_SCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 3) 327*d5cda142SChengci.Xu #define M4U_PORT_L14_SCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 4) 328*d5cda142SChengci.Xu #define M4U_PORT_L14_SCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 5) 329*d5cda142SChengci.Xu #define M4U_PORT_L14_PDAI_B_0 MTK_M4U_ID(SMI_L14_ID, 6) 330*d5cda142SChengci.Xu #define M4U_PORT_L14_PDAI_B_1 MTK_M4U_ID(SMI_L14_ID, 7) 331*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_D_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 8) 332*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_D_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 9) 333*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_F_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 10) 334*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_F_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 11) 335*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_H_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 12) 336*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_H_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 13) 337*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_B_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 14) 338*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_B_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 15) 339*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_D_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 16) 340*d5cda142SChengci.Xu #define M4U_PORT_L14_GCAMSV_D_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 17) 341*d5cda142SChengci.Xu #define M4U_PORT_L14_PDAO_B MTK_M4U_ID(SMI_L14_ID, 18) 342*d5cda142SChengci.Xu #define M4U_PORT_L14_IPUI MTK_M4U_ID(SMI_L14_ID, 19) 343*d5cda142SChengci.Xu #define M4U_PORT_L14_IPUO MTK_M4U_ID(SMI_L14_ID, 20) 344*d5cda142SChengci.Xu #define M4U_PORT_L14_IPU3O MTK_M4U_ID(SMI_L14_ID, 21) 345*d5cda142SChengci.Xu #define M4U_PORT_L14_FAKE MTK_M4U_ID(SMI_L14_ID, 22) 346*d5cda142SChengci.Xu 347*d5cda142SChengci.Xu /* LARB 15 -- IMG-D */ 348*d5cda142SChengci.Xu #define M4U_PORT_L15_VIPI_D1 MTK_M4U_ID(SMI_L15_ID, 0) 349*d5cda142SChengci.Xu #define M4U_PORT_L15_VIPBI_D1 MTK_M4U_ID(SMI_L15_ID, 1) 350*d5cda142SChengci.Xu #define M4U_PORT_L15_SMTI_D6 MTK_M4U_ID(SMI_L15_ID, 2) 351*d5cda142SChengci.Xu #define M4U_PORT_L15_TNCSTI_D1 MTK_M4U_ID(SMI_L15_ID, 3) 352*d5cda142SChengci.Xu #define M4U_PORT_L15_TNCSTI_D4 MTK_M4U_ID(SMI_L15_ID, 4) 353*d5cda142SChengci.Xu #define M4U_PORT_L15_SMTI_D4 MTK_M4U_ID(SMI_L15_ID, 5) 354*d5cda142SChengci.Xu #define M4U_PORT_L15_IMG3O_D1 MTK_M4U_ID(SMI_L15_ID, 6) 355*d5cda142SChengci.Xu #define M4U_PORT_L15_IMG3BO_D1 MTK_M4U_ID(SMI_L15_ID, 7) 356*d5cda142SChengci.Xu #define M4U_PORT_L15_IMG3CO_D1 MTK_M4U_ID(SMI_L15_ID, 8) 357*d5cda142SChengci.Xu #define M4U_PORT_L15_IMG2O_D1 MTK_M4U_ID(SMI_L15_ID, 9) 358*d5cda142SChengci.Xu #define M4U_PORT_L15_SMTI_D9 MTK_M4U_ID(SMI_L15_ID, 10) 359*d5cda142SChengci.Xu #define M4U_PORT_L15_SMTO_D4 MTK_M4U_ID(SMI_L15_ID, 11) 360*d5cda142SChengci.Xu #define M4U_PORT_L15_FEO_D1 MTK_M4U_ID(SMI_L15_ID, 12) 361*d5cda142SChengci.Xu #define M4U_PORT_L15_TNCSO_D1 MTK_M4U_ID(SMI_L15_ID, 13) 362*d5cda142SChengci.Xu #define M4U_PORT_L15_TNCSTO_D1 MTK_M4U_ID(SMI_L15_ID, 14) 363*d5cda142SChengci.Xu #define M4U_PORT_L15_SMTO_D6 MTK_M4U_ID(SMI_L15_ID, 15) 364*d5cda142SChengci.Xu #define M4U_PORT_L15_SMTO_D9 MTK_M4U_ID(SMI_L15_ID, 16) 365*d5cda142SChengci.Xu #define M4U_PORT_L15_TNCO_D1 MTK_M4U_ID(SMI_L15_ID, 17) 366*d5cda142SChengci.Xu #define M4U_PORT_L15_TNCO_D1_N MTK_M4U_ID(SMI_L15_ID, 18) 367*d5cda142SChengci.Xu 368*d5cda142SChengci.Xu /* LARB 16A -- CAM */ 369*d5cda142SChengci.Xu #define M4U_PORT_L16A_IMGO_R1 MTK_M4U_ID(SMI_L16A_ID, 0) 370*d5cda142SChengci.Xu #define M4U_PORT_L16A_CQI_R1 MTK_M4U_ID(SMI_L16A_ID, 1) 371*d5cda142SChengci.Xu #define M4U_PORT_L16A_CQI_R2 MTK_M4U_ID(SMI_L16A_ID, 2) 372*d5cda142SChengci.Xu #define M4U_PORT_L16A_BPCI_R1 MTK_M4U_ID(SMI_L16A_ID, 3) 373*d5cda142SChengci.Xu #define M4U_PORT_L16A_LSCI_R1 MTK_M4U_ID(SMI_L16A_ID, 4) 374*d5cda142SChengci.Xu #define M4U_PORT_L16A_RAWI_R2 MTK_M4U_ID(SMI_L16A_ID, 5) 375*d5cda142SChengci.Xu #define M4U_PORT_L16A_RAWI_R3 MTK_M4U_ID(SMI_L16A_ID, 6) 376*d5cda142SChengci.Xu #define M4U_PORT_L16A_UFDI_R2 MTK_M4U_ID(SMI_L16A_ID, 7) 377*d5cda142SChengci.Xu #define M4U_PORT_L16A_UFDI_R3 MTK_M4U_ID(SMI_L16A_ID, 8) 378*d5cda142SChengci.Xu #define M4U_PORT_L16A_RAWI_R4 MTK_M4U_ID(SMI_L16A_ID, 9) 379*d5cda142SChengci.Xu #define M4U_PORT_L16A_RAWI_R5 MTK_M4U_ID(SMI_L16A_ID, 10) 380*d5cda142SChengci.Xu #define M4U_PORT_L16A_AAI_R1 MTK_M4U_ID(SMI_L16A_ID, 11) 381*d5cda142SChengci.Xu #define M4U_PORT_L16A_UFDI_R5 MTK_M4U_ID(SMI_L16A_ID, 12) 382*d5cda142SChengci.Xu #define M4U_PORT_L16A_FHO_R1 MTK_M4U_ID(SMI_L16A_ID, 13) 383*d5cda142SChengci.Xu #define M4U_PORT_L16A_AAO_R1 MTK_M4U_ID(SMI_L16A_ID, 14) 384*d5cda142SChengci.Xu #define M4U_PORT_L16A_TSFSO_R1 MTK_M4U_ID(SMI_L16A_ID, 15) 385*d5cda142SChengci.Xu #define M4U_PORT_L16A_FLKO_R1 MTK_M4U_ID(SMI_L16A_ID, 16) 386*d5cda142SChengci.Xu 387*d5cda142SChengci.Xu /* LARB 16B -- CAM */ 388*d5cda142SChengci.Xu #define M4U_PORT_L16B_IMGO_R1 MTK_M4U_ID(SMI_L16B_ID, 0) 389*d5cda142SChengci.Xu #define M4U_PORT_L16B_CQI_R1 MTK_M4U_ID(SMI_L16B_ID, 1) 390*d5cda142SChengci.Xu #define M4U_PORT_L16B_CQI_R2 MTK_M4U_ID(SMI_L16B_ID, 2) 391*d5cda142SChengci.Xu #define M4U_PORT_L16B_BPCI_R1 MTK_M4U_ID(SMI_L16B_ID, 3) 392*d5cda142SChengci.Xu #define M4U_PORT_L16B_LSCI_R1 MTK_M4U_ID(SMI_L16B_ID, 4) 393*d5cda142SChengci.Xu #define M4U_PORT_L16B_RAWI_R2 MTK_M4U_ID(SMI_L16B_ID, 5) 394*d5cda142SChengci.Xu #define M4U_PORT_L16B_RAWI_R3 MTK_M4U_ID(SMI_L16B_ID, 6) 395*d5cda142SChengci.Xu #define M4U_PORT_L16B_UFDI_R2 MTK_M4U_ID(SMI_L16B_ID, 7) 396*d5cda142SChengci.Xu #define M4U_PORT_L16B_UFDI_R3 MTK_M4U_ID(SMI_L16B_ID, 8) 397*d5cda142SChengci.Xu #define M4U_PORT_L16B_RAWI_R4 MTK_M4U_ID(SMI_L16B_ID, 9) 398*d5cda142SChengci.Xu #define M4U_PORT_L16B_RAWI_R5 MTK_M4U_ID(SMI_L16B_ID, 10) 399*d5cda142SChengci.Xu #define M4U_PORT_L16B_AAI_R1 MTK_M4U_ID(SMI_L16B_ID, 11) 400*d5cda142SChengci.Xu #define M4U_PORT_L16B_UFDI_R5 MTK_M4U_ID(SMI_L16B_ID, 12) 401*d5cda142SChengci.Xu #define M4U_PORT_L16B_FHO_R1 MTK_M4U_ID(SMI_L16B_ID, 13) 402*d5cda142SChengci.Xu #define M4U_PORT_L16B_AAO_R1 MTK_M4U_ID(SMI_L16B_ID, 14) 403*d5cda142SChengci.Xu #define M4U_PORT_L16B_TSFSO_R1 MTK_M4U_ID(SMI_L16B_ID, 15) 404*d5cda142SChengci.Xu #define M4U_PORT_L16B_FLKO_R1 MTK_M4U_ID(SMI_L16B_ID, 16) 405*d5cda142SChengci.Xu 406*d5cda142SChengci.Xu /* LARB 17A -- CAM */ 407*d5cda142SChengci.Xu #define M4U_PORT_L17A_YUVO_R1 MTK_M4U_ID(SMI_L17A_ID, 0) 408*d5cda142SChengci.Xu #define M4U_PORT_L17A_YUVO_R3 MTK_M4U_ID(SMI_L17A_ID, 1) 409*d5cda142SChengci.Xu #define M4U_PORT_L17A_YUVCO_R1 MTK_M4U_ID(SMI_L17A_ID, 2) 410*d5cda142SChengci.Xu #define M4U_PORT_L17A_YUVO_R2 MTK_M4U_ID(SMI_L17A_ID, 3) 411*d5cda142SChengci.Xu #define M4U_PORT_L17A_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17A_ID, 4) 412*d5cda142SChengci.Xu #define M4U_PORT_L17A_DRZS4NO_R1 MTK_M4U_ID(SMI_L17A_ID, 5) 413*d5cda142SChengci.Xu #define M4U_PORT_L17A_TNCSO_R1 MTK_M4U_ID(SMI_L17A_ID, 6) 414*d5cda142SChengci.Xu 415*d5cda142SChengci.Xu /* LARB 17B -- CAM */ 416*d5cda142SChengci.Xu #define M4U_PORT_L17B_YUVO_R1 MTK_M4U_ID(SMI_L17B_ID, 0) 417*d5cda142SChengci.Xu #define M4U_PORT_L17B_YUVO_R3 MTK_M4U_ID(SMI_L17B_ID, 1) 418*d5cda142SChengci.Xu #define M4U_PORT_L17B_YUVCO_R1 MTK_M4U_ID(SMI_L17B_ID, 2) 419*d5cda142SChengci.Xu #define M4U_PORT_L17B_YUVO_R2 MTK_M4U_ID(SMI_L17B_ID, 3) 420*d5cda142SChengci.Xu #define M4U_PORT_L17B_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17B_ID, 4) 421*d5cda142SChengci.Xu #define M4U_PORT_L17B_DRZS4NO_R1 MTK_M4U_ID(SMI_L17B_ID, 5) 422*d5cda142SChengci.Xu #define M4U_PORT_L17B_TNCSO_R1 MTK_M4U_ID(SMI_L17B_ID, 6) 423*d5cda142SChengci.Xu 424*d5cda142SChengci.Xu /* LARB 19 -- VENC */ 425*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(SMI_L19_ID, 0) 426*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_REC MTK_M4U_ID(SMI_L19_ID, 1) 427*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 2) 428*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(SMI_L19_ID, 3) 429*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(SMI_L19_ID, 4) 430*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 5) 431*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(SMI_L19_ID, 6) 432*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L19_ID, 7) 433*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(SMI_L19_ID, 8) 434*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(SMI_L19_ID, 9) 435*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L19_ID, 10) 436*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 11) 437*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 12) 438*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGDEC_WDMA_0 MTK_M4U_ID(SMI_L19_ID, 13) 439*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGDEC_BSDMA_0 MTK_M4U_ID(SMI_L19_ID, 14) 440*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 15) 441*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(SMI_L19_ID, 16) 442*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 17) 443*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGDEC_WDMA_1 MTK_M4U_ID(SMI_L19_ID, 18) 444*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGDEC_BSDMA_1 MTK_M4U_ID(SMI_L19_ID, 19) 445*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1 MTK_M4U_ID(SMI_L19_ID, 20) 446*d5cda142SChengci.Xu #define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0 MTK_M4U_ID(SMI_L19_ID, 21) 447*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(SMI_L19_ID, 22) 448*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L19_ID, 23) 449*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(SMI_L19_ID, 24) 450*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(SMI_L19_ID, 25) 451*d5cda142SChengci.Xu #define M4U_PORT_L19_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L19_ID, 26) 452*d5cda142SChengci.Xu 453*d5cda142SChengci.Xu /* LARB 21 -- VDEC-CORE0 */ 454*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L21_ID, 0) 455*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L21_ID, 1) 456*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L21_ID, 2) 457*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L21_ID, 3) 458*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L21_ID, 4) 459*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L21_ID, 5) 460*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L21_ID, 6) 461*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L21_ID, 7) 462*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L21_ID, 8) 463*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L21_ID, 9) 464*d5cda142SChengci.Xu #define M4U_PORT_L21_HW_VDEC_UFO_EXT_C MTK_M4U_ID(SMI_L21_ID, 10) 465*d5cda142SChengci.Xu 466*d5cda142SChengci.Xu /* LARB 23 -- VDEC-SOC */ 467*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT MTK_M4U_ID(SMI_L23_ID, 0) 468*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(SMI_L23_ID, 1) 469*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(SMI_L23_ID, 2) 470*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(SMI_L23_ID, 3) 471*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT MTK_M4U_ID(SMI_L23_ID, 4) 472*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(SMI_L23_ID, 5) 473*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L23_ID, 6) 474*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C MTK_M4U_ID(SMI_L23_ID, 7) 475*d5cda142SChengci.Xu #define M4U_PORT_L23_HW_VDEC_MC_EXT_C MTK_M4U_ID(SMI_L23_ID, 8) 476*d5cda142SChengci.Xu 477*d5cda142SChengci.Xu /* LARB 27 -- CCU */ 478*d5cda142SChengci.Xu #define M4U_PORT_L27_CCUI MTK_M4U_ID(SMI_L27_ID, 0) 479*d5cda142SChengci.Xu #define M4U_PORT_L27_CCUO MTK_M4U_ID(SMI_L27_ID, 1) 480*d5cda142SChengci.Xu #define M4U_PORT_L27_CCUI2 MTK_M4U_ID(SMI_L27_ID, 2) 481*d5cda142SChengci.Xu #define M4U_PORT_L27_CCUO2 MTK_M4U_ID(SMI_L27_ID, 3) 482*d5cda142SChengci.Xu 483*d5cda142SChengci.Xu /* LARB 28 -- AXI-CCU */ 484*d5cda142SChengci.Xu #define M4U_PORT_L28_CCU_AXI_0 MTK_M4U_ID(SMI_L28_ID, 0) 485*d5cda142SChengci.Xu 486*d5cda142SChengci.Xu /* infra/peri */ 487*d5cda142SChengci.Xu #define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0) 488*d5cda142SChengci.Xu 489*d5cda142SChengci.Xu #endif 490