1 /* 2 * Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H 15 #define _DT_BINDINGS_QCOM_SPMI_VADC_H 16 17 /* Voltage ADC channels */ 18 #define VADC_USBIN 0x00 19 #define VADC_DCIN 0x01 20 #define VADC_VCHG_SNS 0x02 21 #define VADC_SPARE1_03 0x03 22 #define VADC_USB_ID_MV 0x04 23 #define VADC_VCOIN 0x05 24 #define VADC_VBAT_SNS 0x06 25 #define VADC_VSYS 0x07 26 #define VADC_DIE_TEMP 0x08 27 #define VADC_REF_625MV 0x09 28 #define VADC_REF_1250MV 0x0a 29 #define VADC_CHG_TEMP 0x0b 30 #define VADC_SPARE1 0x0c 31 #define VADC_SPARE2 0x0d 32 #define VADC_GND_REF 0x0e 33 #define VADC_VDD_VADC 0x0f 34 35 #define VADC_P_MUX1_1_1 0x10 36 #define VADC_P_MUX2_1_1 0x11 37 #define VADC_P_MUX3_1_1 0x12 38 #define VADC_P_MUX4_1_1 0x13 39 #define VADC_P_MUX5_1_1 0x14 40 #define VADC_P_MUX6_1_1 0x15 41 #define VADC_P_MUX7_1_1 0x16 42 #define VADC_P_MUX8_1_1 0x17 43 #define VADC_P_MUX9_1_1 0x18 44 #define VADC_P_MUX10_1_1 0x19 45 #define VADC_P_MUX11_1_1 0x1a 46 #define VADC_P_MUX12_1_1 0x1b 47 #define VADC_P_MUX13_1_1 0x1c 48 #define VADC_P_MUX14_1_1 0x1d 49 #define VADC_P_MUX15_1_1 0x1e 50 #define VADC_P_MUX16_1_1 0x1f 51 52 #define VADC_P_MUX1_1_3 0x20 53 #define VADC_P_MUX2_1_3 0x21 54 #define VADC_P_MUX3_1_3 0x22 55 #define VADC_P_MUX4_1_3 0x23 56 #define VADC_P_MUX5_1_3 0x24 57 #define VADC_P_MUX6_1_3 0x25 58 #define VADC_P_MUX7_1_3 0x26 59 #define VADC_P_MUX8_1_3 0x27 60 #define VADC_P_MUX9_1_3 0x28 61 #define VADC_P_MUX10_1_3 0x29 62 #define VADC_P_MUX11_1_3 0x2a 63 #define VADC_P_MUX12_1_3 0x2b 64 #define VADC_P_MUX13_1_3 0x2c 65 #define VADC_P_MUX14_1_3 0x2d 66 #define VADC_P_MUX15_1_3 0x2e 67 #define VADC_P_MUX16_1_3 0x2f 68 69 #define VADC_LR_MUX1_BAT_THERM 0x30 70 #define VADC_LR_MUX2_BAT_ID 0x31 71 #define VADC_LR_MUX3_XO_THERM 0x32 72 #define VADC_LR_MUX4_AMUX_THM1 0x33 73 #define VADC_LR_MUX5_AMUX_THM2 0x34 74 #define VADC_LR_MUX6_AMUX_THM3 0x35 75 #define VADC_LR_MUX7_HW_ID 0x36 76 #define VADC_LR_MUX8_AMUX_THM4 0x37 77 #define VADC_LR_MUX9_AMUX_THM5 0x38 78 #define VADC_LR_MUX10_USB_ID 0x39 79 #define VADC_AMUX_PU1 0x3a 80 #define VADC_AMUX_PU2 0x3b 81 #define VADC_LR_MUX3_BUF_XO_THERM 0x3c 82 83 #define VADC_LR_MUX1_PU1_BAT_THERM 0x70 84 #define VADC_LR_MUX2_PU1_BAT_ID 0x71 85 #define VADC_LR_MUX3_PU1_XO_THERM 0x72 86 #define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 87 #define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 88 #define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 89 #define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 90 #define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 91 #define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 92 #define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 93 #define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c 94 95 #define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 96 #define VADC_LR_MUX2_PU2_BAT_ID 0xb1 97 #define VADC_LR_MUX3_PU2_XO_THERM 0xb2 98 #define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 99 #define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 100 #define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 101 #define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 102 #define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 103 #define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 104 #define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 105 #define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc 106 107 #define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 108 #define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 109 #define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 110 #define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 111 #define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 112 #define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 113 #define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 114 #define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 115 #define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 116 #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 117 #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc 118 119 /* ADC channels for SPMI PMIC5 */ 120 121 #define ADC5_REF_GND 0x00 122 #define ADC5_1P25VREF 0x01 123 #define ADC5_VREF_VADC 0x02 124 #define ADC5_VREF_VADC5_DIV_3 0x82 125 #define ADC5_VPH_PWR 0x83 126 #define ADC5_VBAT_SNS 0x84 127 #define ADC5_VCOIN 0x85 128 #define ADC5_DIE_TEMP 0x06 129 #define ADC5_USB_IN_I 0x07 130 #define ADC5_USB_IN_V_16 0x08 131 #define ADC5_CHG_TEMP 0x09 132 #define ADC5_BAT_THERM 0x0a 133 #define ADC5_BAT_ID 0x0b 134 #define ADC5_XO_THERM 0x0c 135 #define ADC5_AMUX_THM1 0x0d 136 #define ADC5_AMUX_THM2 0x0e 137 #define ADC5_AMUX_THM3 0x0f 138 #define ADC5_AMUX_THM4 0x10 139 #define ADC5_AMUX_THM5 0x11 140 #define ADC5_GPIO1 0x12 141 #define ADC5_GPIO2 0x13 142 #define ADC5_GPIO3 0x14 143 #define ADC5_GPIO4 0x15 144 #define ADC5_GPIO5 0x16 145 #define ADC5_GPIO6 0x17 146 #define ADC5_GPIO7 0x18 147 #define ADC5_SBUx 0x99 148 #define ADC5_MID_CHG_DIV6 0x1e 149 #define ADC5_OFF 0xff 150 151 /* 30k pull-up1 */ 152 #define ADC5_BAT_THERM_30K_PU 0x2a 153 #define ADC5_BAT_ID_30K_PU 0x2b 154 #define ADC5_XO_THERM_30K_PU 0x2c 155 #define ADC5_AMUX_THM1_30K_PU 0x2d 156 #define ADC5_AMUX_THM2_30K_PU 0x2e 157 #define ADC5_AMUX_THM3_30K_PU 0x2f 158 #define ADC5_AMUX_THM4_30K_PU 0x30 159 #define ADC5_AMUX_THM5_30K_PU 0x31 160 #define ADC5_GPIO1_30K_PU 0x32 161 #define ADC5_GPIO2_30K_PU 0x33 162 #define ADC5_GPIO3_30K_PU 0x34 163 #define ADC5_GPIO4_30K_PU 0x35 164 #define ADC5_GPIO5_30K_PU 0x36 165 #define ADC5_GPIO6_30K_PU 0x37 166 #define ADC5_GPIO7_30K_PU 0x38 167 #define ADC5_SBUx_30K_PU 0x39 168 169 /* 100k pull-up2 */ 170 #define ADC5_BAT_THERM_100K_PU 0x4a 171 #define ADC5_BAT_ID_100K_PU 0x4b 172 #define ADC5_XO_THERM_100K_PU 0x4c 173 #define ADC5_AMUX_THM1_100K_PU 0x4d 174 #define ADC5_AMUX_THM2_100K_PU 0x4e 175 #define ADC5_AMUX_THM3_100K_PU 0x4f 176 #define ADC5_AMUX_THM4_100K_PU 0x50 177 #define ADC5_AMUX_THM5_100K_PU 0x51 178 #define ADC5_GPIO1_100K_PU 0x52 179 #define ADC5_GPIO2_100K_PU 0x53 180 #define ADC5_GPIO3_100K_PU 0x54 181 #define ADC5_GPIO4_100K_PU 0x55 182 #define ADC5_GPIO5_100K_PU 0x56 183 #define ADC5_GPIO6_100K_PU 0x57 184 #define ADC5_GPIO7_100K_PU 0x58 185 #define ADC5_SBUx_100K_PU 0x59 186 187 /* 400k pull-up3 */ 188 #define ADC5_BAT_THERM_400K_PU 0x6a 189 #define ADC5_BAT_ID_400K_PU 0x6b 190 #define ADC5_XO_THERM_400K_PU 0x6c 191 #define ADC5_AMUX_THM1_400K_PU 0x6d 192 #define ADC5_AMUX_THM2_400K_PU 0x6e 193 #define ADC5_AMUX_THM3_400K_PU 0x6f 194 #define ADC5_AMUX_THM4_400K_PU 0x70 195 #define ADC5_AMUX_THM5_400K_PU 0x71 196 #define ADC5_GPIO1_400K_PU 0x72 197 #define ADC5_GPIO2_400K_PU 0x73 198 #define ADC5_GPIO3_400K_PU 0x74 199 #define ADC5_GPIO4_400K_PU 0x75 200 #define ADC5_GPIO5_400K_PU 0x76 201 #define ADC5_GPIO6_400K_PU 0x77 202 #define ADC5_GPIO7_400K_PU 0x78 203 #define ADC5_SBUx_400K_PU 0x79 204 205 /* 1/3 Divider */ 206 #define ADC5_GPIO1_DIV3 0x92 207 #define ADC5_GPIO2_DIV3 0x93 208 #define ADC5_GPIO3_DIV3 0x94 209 #define ADC5_GPIO4_DIV3 0x95 210 #define ADC5_GPIO5_DIV3 0x96 211 #define ADC5_GPIO6_DIV3 0x97 212 #define ADC5_GPIO7_DIV3 0x98 213 #define ADC5_SBUx_DIV3 0x99 214 215 /* Current and combined current/voltage channels */ 216 #define ADC5_INT_EXT_ISENSE 0xa1 217 #define ADC5_PARALLEL_ISENSE 0xa5 218 #define ADC5_CUR_REPLICA_VDS 0xa7 219 #define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 220 #define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab 221 #define ADC5_EXT_SENS_OFFSET 0xad 222 223 #define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 224 #define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 225 #define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 226 #define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 227 #define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 228 #define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 229 230 #define ADC5_MAX_CHANNEL 0xc0 231 232 #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ 233