1d3ba5586SStanimir Varbanov /* 22fca5855SSiddartha Mohanadoss * Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved. 3d3ba5586SStanimir Varbanov * 4d3ba5586SStanimir Varbanov * This program is free software; you can redistribute it and/or modify 5d3ba5586SStanimir Varbanov * it under the terms of the GNU General Public License version 2 and 6d3ba5586SStanimir Varbanov * only version 2 as published by the Free Software Foundation. 7d3ba5586SStanimir Varbanov * 8d3ba5586SStanimir Varbanov * This program is distributed in the hope that it will be useful 9d3ba5586SStanimir Varbanov * but WITHOUT ANY WARRANTY; without even the implied warranty of 10d3ba5586SStanimir Varbanov * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11d3ba5586SStanimir Varbanov * GNU General Public License for more details. 12d3ba5586SStanimir Varbanov */ 13d3ba5586SStanimir Varbanov 14d3ba5586SStanimir Varbanov #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H 15d3ba5586SStanimir Varbanov #define _DT_BINDINGS_QCOM_SPMI_VADC_H 16d3ba5586SStanimir Varbanov 17d3ba5586SStanimir Varbanov /* Voltage ADC channels */ 18d3ba5586SStanimir Varbanov #define VADC_USBIN 0x00 19d3ba5586SStanimir Varbanov #define VADC_DCIN 0x01 20d3ba5586SStanimir Varbanov #define VADC_VCHG_SNS 0x02 21d3ba5586SStanimir Varbanov #define VADC_SPARE1_03 0x03 22d3ba5586SStanimir Varbanov #define VADC_USB_ID_MV 0x04 23d3ba5586SStanimir Varbanov #define VADC_VCOIN 0x05 24d3ba5586SStanimir Varbanov #define VADC_VBAT_SNS 0x06 25d3ba5586SStanimir Varbanov #define VADC_VSYS 0x07 26d3ba5586SStanimir Varbanov #define VADC_DIE_TEMP 0x08 27d3ba5586SStanimir Varbanov #define VADC_REF_625MV 0x09 28d3ba5586SStanimir Varbanov #define VADC_REF_1250MV 0x0a 29d3ba5586SStanimir Varbanov #define VADC_CHG_TEMP 0x0b 30d3ba5586SStanimir Varbanov #define VADC_SPARE1 0x0c 31d3ba5586SStanimir Varbanov #define VADC_SPARE2 0x0d 32d3ba5586SStanimir Varbanov #define VADC_GND_REF 0x0e 33d3ba5586SStanimir Varbanov #define VADC_VDD_VADC 0x0f 34d3ba5586SStanimir Varbanov 35d3ba5586SStanimir Varbanov #define VADC_P_MUX1_1_1 0x10 36d3ba5586SStanimir Varbanov #define VADC_P_MUX2_1_1 0x11 37d3ba5586SStanimir Varbanov #define VADC_P_MUX3_1_1 0x12 38d3ba5586SStanimir Varbanov #define VADC_P_MUX4_1_1 0x13 39d3ba5586SStanimir Varbanov #define VADC_P_MUX5_1_1 0x14 40d3ba5586SStanimir Varbanov #define VADC_P_MUX6_1_1 0x15 41d3ba5586SStanimir Varbanov #define VADC_P_MUX7_1_1 0x16 42d3ba5586SStanimir Varbanov #define VADC_P_MUX8_1_1 0x17 43d3ba5586SStanimir Varbanov #define VADC_P_MUX9_1_1 0x18 44d3ba5586SStanimir Varbanov #define VADC_P_MUX10_1_1 0x19 45d3ba5586SStanimir Varbanov #define VADC_P_MUX11_1_1 0x1a 46d3ba5586SStanimir Varbanov #define VADC_P_MUX12_1_1 0x1b 47d3ba5586SStanimir Varbanov #define VADC_P_MUX13_1_1 0x1c 48d3ba5586SStanimir Varbanov #define VADC_P_MUX14_1_1 0x1d 49d3ba5586SStanimir Varbanov #define VADC_P_MUX15_1_1 0x1e 50d3ba5586SStanimir Varbanov #define VADC_P_MUX16_1_1 0x1f 51d3ba5586SStanimir Varbanov 52d3ba5586SStanimir Varbanov #define VADC_P_MUX1_1_3 0x20 53d3ba5586SStanimir Varbanov #define VADC_P_MUX2_1_3 0x21 54d3ba5586SStanimir Varbanov #define VADC_P_MUX3_1_3 0x22 55d3ba5586SStanimir Varbanov #define VADC_P_MUX4_1_3 0x23 56d3ba5586SStanimir Varbanov #define VADC_P_MUX5_1_3 0x24 57d3ba5586SStanimir Varbanov #define VADC_P_MUX6_1_3 0x25 58d3ba5586SStanimir Varbanov #define VADC_P_MUX7_1_3 0x26 59d3ba5586SStanimir Varbanov #define VADC_P_MUX8_1_3 0x27 60d3ba5586SStanimir Varbanov #define VADC_P_MUX9_1_3 0x28 61d3ba5586SStanimir Varbanov #define VADC_P_MUX10_1_3 0x29 62d3ba5586SStanimir Varbanov #define VADC_P_MUX11_1_3 0x2a 63d3ba5586SStanimir Varbanov #define VADC_P_MUX12_1_3 0x2b 64d3ba5586SStanimir Varbanov #define VADC_P_MUX13_1_3 0x2c 65d3ba5586SStanimir Varbanov #define VADC_P_MUX14_1_3 0x2d 66d3ba5586SStanimir Varbanov #define VADC_P_MUX15_1_3 0x2e 67d3ba5586SStanimir Varbanov #define VADC_P_MUX16_1_3 0x2f 68d3ba5586SStanimir Varbanov 69d3ba5586SStanimir Varbanov #define VADC_LR_MUX1_BAT_THERM 0x30 70d3ba5586SStanimir Varbanov #define VADC_LR_MUX2_BAT_ID 0x31 71d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_XO_THERM 0x32 72d3ba5586SStanimir Varbanov #define VADC_LR_MUX4_AMUX_THM1 0x33 73d3ba5586SStanimir Varbanov #define VADC_LR_MUX5_AMUX_THM2 0x34 74d3ba5586SStanimir Varbanov #define VADC_LR_MUX6_AMUX_THM3 0x35 75d3ba5586SStanimir Varbanov #define VADC_LR_MUX7_HW_ID 0x36 76d3ba5586SStanimir Varbanov #define VADC_LR_MUX8_AMUX_THM4 0x37 77d3ba5586SStanimir Varbanov #define VADC_LR_MUX9_AMUX_THM5 0x38 78d3ba5586SStanimir Varbanov #define VADC_LR_MUX10_USB_ID 0x39 79d3ba5586SStanimir Varbanov #define VADC_AMUX_PU1 0x3a 80d3ba5586SStanimir Varbanov #define VADC_AMUX_PU2 0x3b 81d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_BUF_XO_THERM 0x3c 82d3ba5586SStanimir Varbanov 83d3ba5586SStanimir Varbanov #define VADC_LR_MUX1_PU1_BAT_THERM 0x70 84d3ba5586SStanimir Varbanov #define VADC_LR_MUX2_PU1_BAT_ID 0x71 85d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_PU1_XO_THERM 0x72 86d3ba5586SStanimir Varbanov #define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 87d3ba5586SStanimir Varbanov #define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 88d3ba5586SStanimir Varbanov #define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 89d3ba5586SStanimir Varbanov #define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 90d3ba5586SStanimir Varbanov #define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 91d3ba5586SStanimir Varbanov #define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 92d3ba5586SStanimir Varbanov #define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 93d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c 94d3ba5586SStanimir Varbanov 95d3ba5586SStanimir Varbanov #define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 96d3ba5586SStanimir Varbanov #define VADC_LR_MUX2_PU2_BAT_ID 0xb1 97d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_PU2_XO_THERM 0xb2 98d3ba5586SStanimir Varbanov #define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 99d3ba5586SStanimir Varbanov #define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 100d3ba5586SStanimir Varbanov #define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 101d3ba5586SStanimir Varbanov #define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 102d3ba5586SStanimir Varbanov #define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 103d3ba5586SStanimir Varbanov #define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 104d3ba5586SStanimir Varbanov #define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 105d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc 106d3ba5586SStanimir Varbanov 107d3ba5586SStanimir Varbanov #define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 108d3ba5586SStanimir Varbanov #define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 109d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 110d3ba5586SStanimir Varbanov #define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 111d3ba5586SStanimir Varbanov #define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 112d3ba5586SStanimir Varbanov #define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 113d3ba5586SStanimir Varbanov #define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 114d3ba5586SStanimir Varbanov #define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 115d3ba5586SStanimir Varbanov #define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 116d3ba5586SStanimir Varbanov #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 117d3ba5586SStanimir Varbanov #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc 118d3ba5586SStanimir Varbanov 1192fca5855SSiddartha Mohanadoss /* ADC channels for SPMI PMIC5 */ 1202fca5855SSiddartha Mohanadoss 1212fca5855SSiddartha Mohanadoss #define ADC5_REF_GND 0x00 1222fca5855SSiddartha Mohanadoss #define ADC5_1P25VREF 0x01 1232fca5855SSiddartha Mohanadoss #define ADC5_VREF_VADC 0x02 1242fca5855SSiddartha Mohanadoss #define ADC5_VREF_VADC5_DIV_3 0x82 1252fca5855SSiddartha Mohanadoss #define ADC5_VPH_PWR 0x83 1262fca5855SSiddartha Mohanadoss #define ADC5_VBAT_SNS 0x84 1272fca5855SSiddartha Mohanadoss #define ADC5_VCOIN 0x85 1282fca5855SSiddartha Mohanadoss #define ADC5_DIE_TEMP 0x06 1292fca5855SSiddartha Mohanadoss #define ADC5_USB_IN_I 0x07 1302fca5855SSiddartha Mohanadoss #define ADC5_USB_IN_V_16 0x08 1312fca5855SSiddartha Mohanadoss #define ADC5_CHG_TEMP 0x09 1322fca5855SSiddartha Mohanadoss #define ADC5_BAT_THERM 0x0a 1332fca5855SSiddartha Mohanadoss #define ADC5_BAT_ID 0x0b 1342fca5855SSiddartha Mohanadoss #define ADC5_XO_THERM 0x0c 1352fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM1 0x0d 1362fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM2 0x0e 1372fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM3 0x0f 1382fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM4 0x10 1392fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM5 0x11 1402fca5855SSiddartha Mohanadoss #define ADC5_GPIO1 0x12 1412fca5855SSiddartha Mohanadoss #define ADC5_GPIO2 0x13 1422fca5855SSiddartha Mohanadoss #define ADC5_GPIO3 0x14 1432fca5855SSiddartha Mohanadoss #define ADC5_GPIO4 0x15 1442fca5855SSiddartha Mohanadoss #define ADC5_GPIO5 0x16 1452fca5855SSiddartha Mohanadoss #define ADC5_GPIO6 0x17 1462fca5855SSiddartha Mohanadoss #define ADC5_GPIO7 0x18 1472fca5855SSiddartha Mohanadoss #define ADC5_SBUx 0x99 1482fca5855SSiddartha Mohanadoss #define ADC5_MID_CHG_DIV6 0x1e 1492fca5855SSiddartha Mohanadoss #define ADC5_OFF 0xff 1502fca5855SSiddartha Mohanadoss 1512fca5855SSiddartha Mohanadoss /* 30k pull-up1 */ 1522fca5855SSiddartha Mohanadoss #define ADC5_BAT_THERM_30K_PU 0x2a 1532fca5855SSiddartha Mohanadoss #define ADC5_BAT_ID_30K_PU 0x2b 1542fca5855SSiddartha Mohanadoss #define ADC5_XO_THERM_30K_PU 0x2c 1552fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM1_30K_PU 0x2d 1562fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM2_30K_PU 0x2e 1572fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM3_30K_PU 0x2f 1582fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM4_30K_PU 0x30 1592fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM5_30K_PU 0x31 1602fca5855SSiddartha Mohanadoss #define ADC5_GPIO1_30K_PU 0x32 1612fca5855SSiddartha Mohanadoss #define ADC5_GPIO2_30K_PU 0x33 1622fca5855SSiddartha Mohanadoss #define ADC5_GPIO3_30K_PU 0x34 1632fca5855SSiddartha Mohanadoss #define ADC5_GPIO4_30K_PU 0x35 1642fca5855SSiddartha Mohanadoss #define ADC5_GPIO5_30K_PU 0x36 1652fca5855SSiddartha Mohanadoss #define ADC5_GPIO6_30K_PU 0x37 1662fca5855SSiddartha Mohanadoss #define ADC5_GPIO7_30K_PU 0x38 1672fca5855SSiddartha Mohanadoss #define ADC5_SBUx_30K_PU 0x39 1682fca5855SSiddartha Mohanadoss 1692fca5855SSiddartha Mohanadoss /* 100k pull-up2 */ 1702fca5855SSiddartha Mohanadoss #define ADC5_BAT_THERM_100K_PU 0x4a 1712fca5855SSiddartha Mohanadoss #define ADC5_BAT_ID_100K_PU 0x4b 1722fca5855SSiddartha Mohanadoss #define ADC5_XO_THERM_100K_PU 0x4c 1732fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM1_100K_PU 0x4d 1742fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM2_100K_PU 0x4e 1752fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM3_100K_PU 0x4f 1762fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM4_100K_PU 0x50 1772fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM5_100K_PU 0x51 1782fca5855SSiddartha Mohanadoss #define ADC5_GPIO1_100K_PU 0x52 1792fca5855SSiddartha Mohanadoss #define ADC5_GPIO2_100K_PU 0x53 1802fca5855SSiddartha Mohanadoss #define ADC5_GPIO3_100K_PU 0x54 1812fca5855SSiddartha Mohanadoss #define ADC5_GPIO4_100K_PU 0x55 1822fca5855SSiddartha Mohanadoss #define ADC5_GPIO5_100K_PU 0x56 1832fca5855SSiddartha Mohanadoss #define ADC5_GPIO6_100K_PU 0x57 1842fca5855SSiddartha Mohanadoss #define ADC5_GPIO7_100K_PU 0x58 1852fca5855SSiddartha Mohanadoss #define ADC5_SBUx_100K_PU 0x59 1862fca5855SSiddartha Mohanadoss 1872fca5855SSiddartha Mohanadoss /* 400k pull-up3 */ 1882fca5855SSiddartha Mohanadoss #define ADC5_BAT_THERM_400K_PU 0x6a 1892fca5855SSiddartha Mohanadoss #define ADC5_BAT_ID_400K_PU 0x6b 1902fca5855SSiddartha Mohanadoss #define ADC5_XO_THERM_400K_PU 0x6c 1912fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM1_400K_PU 0x6d 1922fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM2_400K_PU 0x6e 1932fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM3_400K_PU 0x6f 1942fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM4_400K_PU 0x70 1952fca5855SSiddartha Mohanadoss #define ADC5_AMUX_THM5_400K_PU 0x71 1962fca5855SSiddartha Mohanadoss #define ADC5_GPIO1_400K_PU 0x72 1972fca5855SSiddartha Mohanadoss #define ADC5_GPIO2_400K_PU 0x73 1982fca5855SSiddartha Mohanadoss #define ADC5_GPIO3_400K_PU 0x74 1992fca5855SSiddartha Mohanadoss #define ADC5_GPIO4_400K_PU 0x75 2002fca5855SSiddartha Mohanadoss #define ADC5_GPIO5_400K_PU 0x76 2012fca5855SSiddartha Mohanadoss #define ADC5_GPIO6_400K_PU 0x77 2022fca5855SSiddartha Mohanadoss #define ADC5_GPIO7_400K_PU 0x78 2032fca5855SSiddartha Mohanadoss #define ADC5_SBUx_400K_PU 0x79 2042fca5855SSiddartha Mohanadoss 2052fca5855SSiddartha Mohanadoss /* 1/3 Divider */ 2062fca5855SSiddartha Mohanadoss #define ADC5_GPIO1_DIV3 0x92 2072fca5855SSiddartha Mohanadoss #define ADC5_GPIO2_DIV3 0x93 2082fca5855SSiddartha Mohanadoss #define ADC5_GPIO3_DIV3 0x94 2092fca5855SSiddartha Mohanadoss #define ADC5_GPIO4_DIV3 0x95 2102fca5855SSiddartha Mohanadoss #define ADC5_GPIO5_DIV3 0x96 2112fca5855SSiddartha Mohanadoss #define ADC5_GPIO6_DIV3 0x97 2122fca5855SSiddartha Mohanadoss #define ADC5_GPIO7_DIV3 0x98 2132fca5855SSiddartha Mohanadoss #define ADC5_SBUx_DIV3 0x99 2142fca5855SSiddartha Mohanadoss 2152fca5855SSiddartha Mohanadoss /* Current and combined current/voltage channels */ 2162fca5855SSiddartha Mohanadoss #define ADC5_INT_EXT_ISENSE 0xa1 2172fca5855SSiddartha Mohanadoss #define ADC5_PARALLEL_ISENSE 0xa5 2182fca5855SSiddartha Mohanadoss #define ADC5_CUR_REPLICA_VDS 0xa7 2192fca5855SSiddartha Mohanadoss #define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 2202fca5855SSiddartha Mohanadoss #define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab 2212fca5855SSiddartha Mohanadoss #define ADC5_EXT_SENS_OFFSET 0xad 2222fca5855SSiddartha Mohanadoss 2232fca5855SSiddartha Mohanadoss #define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 2242fca5855SSiddartha Mohanadoss #define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 2252fca5855SSiddartha Mohanadoss #define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 2262fca5855SSiddartha Mohanadoss #define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 2272fca5855SSiddartha Mohanadoss #define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 2282fca5855SSiddartha Mohanadoss #define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 2292fca5855SSiddartha Mohanadoss 2302fca5855SSiddartha Mohanadoss #define ADC5_MAX_CHANNEL 0xc0 2312fca5855SSiddartha Mohanadoss 232d3ba5586SStanimir Varbanov #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ 233