1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
4  * Copyright 2017-2018 NXP
5  */
6 
7 #ifndef __DT_BINDINGS_RSCRC_IMX_H
8 #define __DT_BINDINGS_RSCRC_IMX_H
9 
10 /*
11  * These defines are used to indicate a resource. Resources include peripherals
12  * and bus masters (but not memory regions). Note items from list should
13  * never be changed or removed (only added to at the end of the list).
14  */
15 
16 #define IMX_SC_R_A53			0
17 #define IMX_SC_R_A53_0			1
18 #define IMX_SC_R_A53_1			2
19 #define IMX_SC_R_A53_2			3
20 #define IMX_SC_R_A53_3			4
21 #define IMX_SC_R_A72			5
22 #define IMX_SC_R_A72_0			6
23 #define IMX_SC_R_A72_1			7
24 #define IMX_SC_R_A72_2			8
25 #define IMX_SC_R_A72_3			9
26 #define IMX_SC_R_CCI			10
27 #define IMX_SC_R_DB			11
28 #define IMX_SC_R_DRC_0			12
29 #define IMX_SC_R_DRC_1			13
30 #define IMX_SC_R_GIC_SMMU		14
31 #define IMX_SC_R_IRQSTR_M4_0		15
32 #define IMX_SC_R_IRQSTR_M4_1		16
33 #define IMX_SC_R_SMMU			17
34 #define IMX_SC_R_GIC			18
35 #define IMX_SC_R_DC_0_BLIT0		19
36 #define IMX_SC_R_DC_0_BLIT1		20
37 #define IMX_SC_R_DC_0_BLIT2		21
38 #define IMX_SC_R_DC_0_BLIT_OUT		22
39 #define IMX_SC_R_PERF			23
40 #define IMX_SC_R_DC_0_WARP		25
41 #define IMX_SC_R_DC_0_VIDEO0		28
42 #define IMX_SC_R_DC_0_VIDEO1		29
43 #define IMX_SC_R_DC_0_FRAC0		30
44 #define IMX_SC_R_DC_0			32
45 #define IMX_SC_R_GPU_2_PID0		33
46 #define IMX_SC_R_DC_0_PLL_0		34
47 #define IMX_SC_R_DC_0_PLL_1		35
48 #define IMX_SC_R_DC_1_BLIT0		36
49 #define IMX_SC_R_DC_1_BLIT1		37
50 #define IMX_SC_R_DC_1_BLIT2		38
51 #define IMX_SC_R_DC_1_BLIT_OUT		39
52 #define IMX_SC_R_DC_1_WARP		42
53 #define IMX_SC_R_DC_1_VIDEO0		45
54 #define IMX_SC_R_DC_1_VIDEO1		46
55 #define IMX_SC_R_DC_1_FRAC0		47
56 #define IMX_SC_R_DC_1			49
57 #define IMX_SC_R_DC_1_PLL_0		51
58 #define IMX_SC_R_DC_1_PLL_1		52
59 #define IMX_SC_R_SPI_0			53
60 #define IMX_SC_R_SPI_1			54
61 #define IMX_SC_R_SPI_2			55
62 #define IMX_SC_R_SPI_3			56
63 #define IMX_SC_R_UART_0			57
64 #define IMX_SC_R_UART_1			58
65 #define IMX_SC_R_UART_2			59
66 #define IMX_SC_R_UART_3			60
67 #define IMX_SC_R_UART_4			61
68 #define IMX_SC_R_EMVSIM_0		62
69 #define IMX_SC_R_EMVSIM_1		63
70 #define IMX_SC_R_DMA_0_CH0		64
71 #define IMX_SC_R_DMA_0_CH1		65
72 #define IMX_SC_R_DMA_0_CH2		66
73 #define IMX_SC_R_DMA_0_CH3		67
74 #define IMX_SC_R_DMA_0_CH4		68
75 #define IMX_SC_R_DMA_0_CH5		69
76 #define IMX_SC_R_DMA_0_CH6		70
77 #define IMX_SC_R_DMA_0_CH7		71
78 #define IMX_SC_R_DMA_0_CH8		72
79 #define IMX_SC_R_DMA_0_CH9		73
80 #define IMX_SC_R_DMA_0_CH10		74
81 #define IMX_SC_R_DMA_0_CH11		75
82 #define IMX_SC_R_DMA_0_CH12		76
83 #define IMX_SC_R_DMA_0_CH13		77
84 #define IMX_SC_R_DMA_0_CH14		78
85 #define IMX_SC_R_DMA_0_CH15		79
86 #define IMX_SC_R_DMA_0_CH16		80
87 #define IMX_SC_R_DMA_0_CH17		81
88 #define IMX_SC_R_DMA_0_CH18		82
89 #define IMX_SC_R_DMA_0_CH19		83
90 #define IMX_SC_R_DMA_0_CH20		84
91 #define IMX_SC_R_DMA_0_CH21		85
92 #define IMX_SC_R_DMA_0_CH22		86
93 #define IMX_SC_R_DMA_0_CH23		87
94 #define IMX_SC_R_DMA_0_CH24		88
95 #define IMX_SC_R_DMA_0_CH25		89
96 #define IMX_SC_R_DMA_0_CH26		90
97 #define IMX_SC_R_DMA_0_CH27		91
98 #define IMX_SC_R_DMA_0_CH28		92
99 #define IMX_SC_R_DMA_0_CH29		93
100 #define IMX_SC_R_DMA_0_CH30		94
101 #define IMX_SC_R_DMA_0_CH31		95
102 #define IMX_SC_R_I2C_0			96
103 #define IMX_SC_R_I2C_1			97
104 #define IMX_SC_R_I2C_2			98
105 #define IMX_SC_R_I2C_3			99
106 #define IMX_SC_R_I2C_4			100
107 #define IMX_SC_R_ADC_0			101
108 #define IMX_SC_R_ADC_1			102
109 #define IMX_SC_R_FTM_0			103
110 #define IMX_SC_R_FTM_1			104
111 #define IMX_SC_R_CAN_0			105
112 #define IMX_SC_R_CAN_1			106
113 #define IMX_SC_R_CAN_2			107
114 #define IMX_SC_R_DMA_1_CH0		108
115 #define IMX_SC_R_DMA_1_CH1		109
116 #define IMX_SC_R_DMA_1_CH2		110
117 #define IMX_SC_R_DMA_1_CH3		111
118 #define IMX_SC_R_DMA_1_CH4		112
119 #define IMX_SC_R_DMA_1_CH5		113
120 #define IMX_SC_R_DMA_1_CH6		114
121 #define IMX_SC_R_DMA_1_CH7		115
122 #define IMX_SC_R_DMA_1_CH8		116
123 #define IMX_SC_R_DMA_1_CH9		117
124 #define IMX_SC_R_DMA_1_CH10		118
125 #define IMX_SC_R_DMA_1_CH11		119
126 #define IMX_SC_R_DMA_1_CH12		120
127 #define IMX_SC_R_DMA_1_CH13		121
128 #define IMX_SC_R_DMA_1_CH14		122
129 #define IMX_SC_R_DMA_1_CH15		123
130 #define IMX_SC_R_DMA_1_CH16		124
131 #define IMX_SC_R_DMA_1_CH17		125
132 #define IMX_SC_R_DMA_1_CH18		126
133 #define IMX_SC_R_DMA_1_CH19		127
134 #define IMX_SC_R_DMA_1_CH20		128
135 #define IMX_SC_R_DMA_1_CH21		129
136 #define IMX_SC_R_DMA_1_CH22		130
137 #define IMX_SC_R_DMA_1_CH23		131
138 #define IMX_SC_R_DMA_1_CH24		132
139 #define IMX_SC_R_DMA_1_CH25		133
140 #define IMX_SC_R_DMA_1_CH26		134
141 #define IMX_SC_R_DMA_1_CH27		135
142 #define IMX_SC_R_DMA_1_CH28		136
143 #define IMX_SC_R_DMA_1_CH29		137
144 #define IMX_SC_R_DMA_1_CH30		138
145 #define IMX_SC_R_DMA_1_CH31		139
146 #define IMX_SC_R_UNUSED1		140
147 #define IMX_SC_R_UNUSED2		141
148 #define IMX_SC_R_UNUSED3		142
149 #define IMX_SC_R_UNUSED4		143
150 #define IMX_SC_R_GPU_0_PID0		144
151 #define IMX_SC_R_GPU_0_PID1		145
152 #define IMX_SC_R_GPU_0_PID2		146
153 #define IMX_SC_R_GPU_0_PID3		147
154 #define IMX_SC_R_GPU_1_PID0		148
155 #define IMX_SC_R_GPU_1_PID1		149
156 #define IMX_SC_R_GPU_1_PID2		150
157 #define IMX_SC_R_GPU_1_PID3		151
158 #define IMX_SC_R_PCIE_A			152
159 #define IMX_SC_R_SERDES_0		153
160 #define IMX_SC_R_MATCH_0		154
161 #define IMX_SC_R_MATCH_1		155
162 #define IMX_SC_R_MATCH_2		156
163 #define IMX_SC_R_MATCH_3		157
164 #define IMX_SC_R_MATCH_4		158
165 #define IMX_SC_R_MATCH_5		159
166 #define IMX_SC_R_MATCH_6		160
167 #define IMX_SC_R_MATCH_7		161
168 #define IMX_SC_R_MATCH_8		162
169 #define IMX_SC_R_MATCH_9		163
170 #define IMX_SC_R_MATCH_10		164
171 #define IMX_SC_R_MATCH_11		165
172 #define IMX_SC_R_MATCH_12		166
173 #define IMX_SC_R_MATCH_13		167
174 #define IMX_SC_R_MATCH_14		168
175 #define IMX_SC_R_PCIE_B			169
176 #define IMX_SC_R_SATA_0			170
177 #define IMX_SC_R_SERDES_1		171
178 #define IMX_SC_R_HSIO_GPIO		172
179 #define IMX_SC_R_MATCH_15		173
180 #define IMX_SC_R_MATCH_16		174
181 #define IMX_SC_R_MATCH_17		175
182 #define IMX_SC_R_MATCH_18		176
183 #define IMX_SC_R_MATCH_19		177
184 #define IMX_SC_R_MATCH_20		178
185 #define IMX_SC_R_MATCH_21		179
186 #define IMX_SC_R_MATCH_22		180
187 #define IMX_SC_R_MATCH_23		181
188 #define IMX_SC_R_MATCH_24		182
189 #define IMX_SC_R_MATCH_25		183
190 #define IMX_SC_R_MATCH_26		184
191 #define IMX_SC_R_MATCH_27		185
192 #define IMX_SC_R_MATCH_28		186
193 #define IMX_SC_R_LCD_0			187
194 #define IMX_SC_R_LCD_0_PWM_0		188
195 #define IMX_SC_R_LCD_0_I2C_0		189
196 #define IMX_SC_R_LCD_0_I2C_1		190
197 #define IMX_SC_R_PWM_0			191
198 #define IMX_SC_R_PWM_1			192
199 #define IMX_SC_R_PWM_2			193
200 #define IMX_SC_R_PWM_3			194
201 #define IMX_SC_R_PWM_4			195
202 #define IMX_SC_R_PWM_5			196
203 #define IMX_SC_R_PWM_6			197
204 #define IMX_SC_R_PWM_7			198
205 #define IMX_SC_R_GPIO_0			199
206 #define IMX_SC_R_GPIO_1			200
207 #define IMX_SC_R_GPIO_2			201
208 #define IMX_SC_R_GPIO_3			202
209 #define IMX_SC_R_GPIO_4			203
210 #define IMX_SC_R_GPIO_5			204
211 #define IMX_SC_R_GPIO_6			205
212 #define IMX_SC_R_GPIO_7			206
213 #define IMX_SC_R_GPT_0			207
214 #define IMX_SC_R_GPT_1			208
215 #define IMX_SC_R_GPT_2			209
216 #define IMX_SC_R_GPT_3			210
217 #define IMX_SC_R_GPT_4			211
218 #define IMX_SC_R_KPP			212
219 #define IMX_SC_R_MU_0A			213
220 #define IMX_SC_R_MU_1A			214
221 #define IMX_SC_R_MU_2A			215
222 #define IMX_SC_R_MU_3A			216
223 #define IMX_SC_R_MU_4A			217
224 #define IMX_SC_R_MU_5A			218
225 #define IMX_SC_R_MU_6A			219
226 #define IMX_SC_R_MU_7A			220
227 #define IMX_SC_R_MU_8A			221
228 #define IMX_SC_R_MU_9A			222
229 #define IMX_SC_R_MU_10A			223
230 #define IMX_SC_R_MU_11A			224
231 #define IMX_SC_R_MU_12A			225
232 #define IMX_SC_R_MU_13A			226
233 #define IMX_SC_R_MU_5B			227
234 #define IMX_SC_R_MU_6B			228
235 #define IMX_SC_R_MU_7B			229
236 #define IMX_SC_R_MU_8B			230
237 #define IMX_SC_R_MU_9B			231
238 #define IMX_SC_R_MU_10B			232
239 #define IMX_SC_R_MU_11B			233
240 #define IMX_SC_R_MU_12B			234
241 #define IMX_SC_R_MU_13B			235
242 #define IMX_SC_R_ROM_0			236
243 #define IMX_SC_R_FSPI_0			237
244 #define IMX_SC_R_FSPI_1			238
245 #define IMX_SC_R_IEE			239
246 #define IMX_SC_R_IEE_R0			240
247 #define IMX_SC_R_IEE_R1			241
248 #define IMX_SC_R_IEE_R2			242
249 #define IMX_SC_R_IEE_R3			243
250 #define IMX_SC_R_IEE_R4			244
251 #define IMX_SC_R_IEE_R5			245
252 #define IMX_SC_R_IEE_R6			246
253 #define IMX_SC_R_IEE_R7			247
254 #define IMX_SC_R_SDHC_0			248
255 #define IMX_SC_R_SDHC_1			249
256 #define IMX_SC_R_SDHC_2			250
257 #define IMX_SC_R_ENET_0			251
258 #define IMX_SC_R_ENET_1			252
259 #define IMX_SC_R_MLB_0			253
260 #define IMX_SC_R_DMA_2_CH0		254
261 #define IMX_SC_R_DMA_2_CH1		255
262 #define IMX_SC_R_DMA_2_CH2		256
263 #define IMX_SC_R_DMA_2_CH3		257
264 #define IMX_SC_R_DMA_2_CH4		258
265 #define IMX_SC_R_USB_0			259
266 #define IMX_SC_R_USB_1			260
267 #define IMX_SC_R_USB_0_PHY		261
268 #define IMX_SC_R_USB_2			262
269 #define IMX_SC_R_USB_2_PHY		263
270 #define IMX_SC_R_DTCP			264
271 #define IMX_SC_R_NAND			265
272 #define IMX_SC_R_LVDS_0			266
273 #define IMX_SC_R_LVDS_0_PWM_0		267
274 #define IMX_SC_R_LVDS_0_I2C_0		268
275 #define IMX_SC_R_LVDS_0_I2C_1		269
276 #define IMX_SC_R_LVDS_1			270
277 #define IMX_SC_R_LVDS_1_PWM_0		271
278 #define IMX_SC_R_LVDS_1_I2C_0		272
279 #define IMX_SC_R_LVDS_1_I2C_1		273
280 #define IMX_SC_R_LVDS_2			274
281 #define IMX_SC_R_LVDS_2_PWM_0		275
282 #define IMX_SC_R_LVDS_2_I2C_0		276
283 #define IMX_SC_R_LVDS_2_I2C_1		277
284 #define IMX_SC_R_M4_0_PID0		278
285 #define IMX_SC_R_M4_0_PID1		279
286 #define IMX_SC_R_M4_0_PID2		280
287 #define IMX_SC_R_M4_0_PID3		281
288 #define IMX_SC_R_M4_0_PID4		282
289 #define IMX_SC_R_M4_0_RGPIO		283
290 #define IMX_SC_R_M4_0_SEMA42		284
291 #define IMX_SC_R_M4_0_TPM		285
292 #define IMX_SC_R_M4_0_PIT		286
293 #define IMX_SC_R_M4_0_UART		287
294 #define IMX_SC_R_M4_0_I2C		288
295 #define IMX_SC_R_M4_0_INTMUX		289
296 #define IMX_SC_R_M4_0_MU_0B		292
297 #define IMX_SC_R_M4_0_MU_0A0		293
298 #define IMX_SC_R_M4_0_MU_0A1		294
299 #define IMX_SC_R_M4_0_MU_0A2		295
300 #define IMX_SC_R_M4_0_MU_0A3		296
301 #define IMX_SC_R_M4_0_MU_1A		297
302 #define IMX_SC_R_M4_1_PID0		298
303 #define IMX_SC_R_M4_1_PID1		299
304 #define IMX_SC_R_M4_1_PID2		300
305 #define IMX_SC_R_M4_1_PID3		301
306 #define IMX_SC_R_M4_1_PID4		302
307 #define IMX_SC_R_M4_1_RGPIO		303
308 #define IMX_SC_R_M4_1_SEMA42		304
309 #define IMX_SC_R_M4_1_TPM		305
310 #define IMX_SC_R_M4_1_PIT		306
311 #define IMX_SC_R_M4_1_UART		307
312 #define IMX_SC_R_M4_1_I2C		308
313 #define IMX_SC_R_M4_1_INTMUX		309
314 #define IMX_SC_R_M4_1_MU_0B		312
315 #define IMX_SC_R_M4_1_MU_0A0		313
316 #define IMX_SC_R_M4_1_MU_0A1		314
317 #define IMX_SC_R_M4_1_MU_0A2		315
318 #define IMX_SC_R_M4_1_MU_0A3		316
319 #define IMX_SC_R_M4_1_MU_1A		317
320 #define IMX_SC_R_SAI_0			318
321 #define IMX_SC_R_SAI_1			319
322 #define IMX_SC_R_SAI_2			320
323 #define IMX_SC_R_IRQSTR_SCU2		321
324 #define IMX_SC_R_IRQSTR_DSP		322
325 #define IMX_SC_R_ELCDIF_PLL		323
326 #define IMX_SC_R_OCRAM			324
327 #define IMX_SC_R_AUDIO_PLL_0		325
328 #define IMX_SC_R_PI_0			326
329 #define IMX_SC_R_PI_0_PWM_0		327
330 #define IMX_SC_R_PI_0_PWM_1		328
331 #define IMX_SC_R_PI_0_I2C_0		329
332 #define IMX_SC_R_PI_0_PLL		330
333 #define IMX_SC_R_PI_1			331
334 #define IMX_SC_R_PI_1_PWM_0		332
335 #define IMX_SC_R_PI_1_PWM_1		333
336 #define IMX_SC_R_PI_1_I2C_0		334
337 #define IMX_SC_R_PI_1_PLL		335
338 #define IMX_SC_R_SC_PID0		336
339 #define IMX_SC_R_SC_PID1		337
340 #define IMX_SC_R_SC_PID2		338
341 #define IMX_SC_R_SC_PID3		339
342 #define IMX_SC_R_SC_PID4		340
343 #define IMX_SC_R_SC_SEMA42		341
344 #define IMX_SC_R_SC_TPM			342
345 #define IMX_SC_R_SC_PIT			343
346 #define IMX_SC_R_SC_UART		344
347 #define IMX_SC_R_SC_I2C			345
348 #define IMX_SC_R_SC_MU_0B		346
349 #define IMX_SC_R_SC_MU_0A0		347
350 #define IMX_SC_R_SC_MU_0A1		348
351 #define IMX_SC_R_SC_MU_0A2		349
352 #define IMX_SC_R_SC_MU_0A3		350
353 #define IMX_SC_R_SC_MU_1A		351
354 #define IMX_SC_R_SYSCNT_RD		352
355 #define IMX_SC_R_SYSCNT_CMP		353
356 #define IMX_SC_R_DEBUG			354
357 #define IMX_SC_R_SYSTEM			355
358 #define IMX_SC_R_SNVS			356
359 #define IMX_SC_R_OTP			357
360 #define IMX_SC_R_VPU_PID0		358
361 #define IMX_SC_R_VPU_PID1		359
362 #define IMX_SC_R_VPU_PID2		360
363 #define IMX_SC_R_VPU_PID3		361
364 #define IMX_SC_R_VPU_PID4		362
365 #define IMX_SC_R_VPU_PID5		363
366 #define IMX_SC_R_VPU_PID6		364
367 #define IMX_SC_R_VPU_PID7		365
368 #define IMX_SC_R_VPU_UART		366
369 #define IMX_SC_R_VPUCORE		367
370 #define IMX_SC_R_VPUCORE_0		368
371 #define IMX_SC_R_VPUCORE_1		369
372 #define IMX_SC_R_VPUCORE_2		370
373 #define IMX_SC_R_VPUCORE_3		371
374 #define IMX_SC_R_DMA_4_CH0		372
375 #define IMX_SC_R_DMA_4_CH1		373
376 #define IMX_SC_R_DMA_4_CH2		374
377 #define IMX_SC_R_DMA_4_CH3		375
378 #define IMX_SC_R_DMA_4_CH4		376
379 #define IMX_SC_R_ISI_CH0		377
380 #define IMX_SC_R_ISI_CH1		378
381 #define IMX_SC_R_ISI_CH2		379
382 #define IMX_SC_R_ISI_CH3		380
383 #define IMX_SC_R_ISI_CH4		381
384 #define IMX_SC_R_ISI_CH5		382
385 #define IMX_SC_R_ISI_CH6		383
386 #define IMX_SC_R_ISI_CH7		384
387 #define IMX_SC_R_MJPEG_DEC_S0		385
388 #define IMX_SC_R_MJPEG_DEC_S1		386
389 #define IMX_SC_R_MJPEG_DEC_S2		387
390 #define IMX_SC_R_MJPEG_DEC_S3		388
391 #define IMX_SC_R_MJPEG_ENC_S0		389
392 #define IMX_SC_R_MJPEG_ENC_S1		390
393 #define IMX_SC_R_MJPEG_ENC_S2		391
394 #define IMX_SC_R_MJPEG_ENC_S3		392
395 #define IMX_SC_R_MIPI_0			393
396 #define IMX_SC_R_MIPI_0_PWM_0		394
397 #define IMX_SC_R_MIPI_0_I2C_0		395
398 #define IMX_SC_R_MIPI_0_I2C_1		396
399 #define IMX_SC_R_MIPI_1			397
400 #define IMX_SC_R_MIPI_1_PWM_0		398
401 #define IMX_SC_R_MIPI_1_I2C_0		399
402 #define IMX_SC_R_MIPI_1_I2C_1		400
403 #define IMX_SC_R_CSI_0			401
404 #define IMX_SC_R_CSI_0_PWM_0		402
405 #define IMX_SC_R_CSI_0_I2C_0		403
406 #define IMX_SC_R_CSI_1			404
407 #define IMX_SC_R_CSI_1_PWM_0		405
408 #define IMX_SC_R_CSI_1_I2C_0		406
409 #define IMX_SC_R_HDMI			407
410 #define IMX_SC_R_HDMI_I2S		408
411 #define IMX_SC_R_HDMI_I2C_0		409
412 #define IMX_SC_R_HDMI_PLL_0		410
413 #define IMX_SC_R_HDMI_RX		411
414 #define IMX_SC_R_HDMI_RX_BYPASS		412
415 #define IMX_SC_R_HDMI_RX_I2C_0		413
416 #define IMX_SC_R_ASRC_0			414
417 #define IMX_SC_R_ESAI_0			415
418 #define IMX_SC_R_SPDIF_0		416
419 #define IMX_SC_R_SPDIF_1		417
420 #define IMX_SC_R_SAI_3			418
421 #define IMX_SC_R_SAI_4			419
422 #define IMX_SC_R_SAI_5			420
423 #define IMX_SC_R_GPT_5			421
424 #define IMX_SC_R_GPT_6			422
425 #define IMX_SC_R_GPT_7			423
426 #define IMX_SC_R_GPT_8			424
427 #define IMX_SC_R_GPT_9			425
428 #define IMX_SC_R_GPT_10			426
429 #define IMX_SC_R_DMA_2_CH5		427
430 #define IMX_SC_R_DMA_2_CH6		428
431 #define IMX_SC_R_DMA_2_CH7		429
432 #define IMX_SC_R_DMA_2_CH8		430
433 #define IMX_SC_R_DMA_2_CH9		431
434 #define IMX_SC_R_DMA_2_CH10		432
435 #define IMX_SC_R_DMA_2_CH11		433
436 #define IMX_SC_R_DMA_2_CH12		434
437 #define IMX_SC_R_DMA_2_CH13		435
438 #define IMX_SC_R_DMA_2_CH14		436
439 #define IMX_SC_R_DMA_2_CH15		437
440 #define IMX_SC_R_DMA_2_CH16		438
441 #define IMX_SC_R_DMA_2_CH17		439
442 #define IMX_SC_R_DMA_2_CH18		440
443 #define IMX_SC_R_DMA_2_CH19		441
444 #define IMX_SC_R_DMA_2_CH20		442
445 #define IMX_SC_R_DMA_2_CH21		443
446 #define IMX_SC_R_DMA_2_CH22		444
447 #define IMX_SC_R_DMA_2_CH23		445
448 #define IMX_SC_R_DMA_2_CH24		446
449 #define IMX_SC_R_DMA_2_CH25		447
450 #define IMX_SC_R_DMA_2_CH26		448
451 #define IMX_SC_R_DMA_2_CH27		449
452 #define IMX_SC_R_DMA_2_CH28		450
453 #define IMX_SC_R_DMA_2_CH29		451
454 #define IMX_SC_R_DMA_2_CH30		452
455 #define IMX_SC_R_DMA_2_CH31		453
456 #define IMX_SC_R_ASRC_1			454
457 #define IMX_SC_R_ESAI_1			455
458 #define IMX_SC_R_SAI_6			456
459 #define IMX_SC_R_SAI_7			457
460 #define IMX_SC_R_AMIX			458
461 #define IMX_SC_R_MQS_0			459
462 #define IMX_SC_R_DMA_3_CH0		460
463 #define IMX_SC_R_DMA_3_CH1		461
464 #define IMX_SC_R_DMA_3_CH2		462
465 #define IMX_SC_R_DMA_3_CH3		463
466 #define IMX_SC_R_DMA_3_CH4		464
467 #define IMX_SC_R_DMA_3_CH5		465
468 #define IMX_SC_R_DMA_3_CH6		466
469 #define IMX_SC_R_DMA_3_CH7		467
470 #define IMX_SC_R_DMA_3_CH8		468
471 #define IMX_SC_R_DMA_3_CH9		469
472 #define IMX_SC_R_DMA_3_CH10		470
473 #define IMX_SC_R_DMA_3_CH11		471
474 #define IMX_SC_R_DMA_3_CH12		472
475 #define IMX_SC_R_DMA_3_CH13		473
476 #define IMX_SC_R_DMA_3_CH14		474
477 #define IMX_SC_R_DMA_3_CH15		475
478 #define IMX_SC_R_DMA_3_CH16		476
479 #define IMX_SC_R_DMA_3_CH17		477
480 #define IMX_SC_R_DMA_3_CH18		478
481 #define IMX_SC_R_DMA_3_CH19		479
482 #define IMX_SC_R_DMA_3_CH20		480
483 #define IMX_SC_R_DMA_3_CH21		481
484 #define IMX_SC_R_DMA_3_CH22		482
485 #define IMX_SC_R_DMA_3_CH23		483
486 #define IMX_SC_R_DMA_3_CH24		484
487 #define IMX_SC_R_DMA_3_CH25		485
488 #define IMX_SC_R_DMA_3_CH26		486
489 #define IMX_SC_R_DMA_3_CH27		487
490 #define IMX_SC_R_DMA_3_CH28		488
491 #define IMX_SC_R_DMA_3_CH29		489
492 #define IMX_SC_R_DMA_3_CH30		490
493 #define IMX_SC_R_DMA_3_CH31		491
494 #define IMX_SC_R_AUDIO_PLL_1		492
495 #define IMX_SC_R_AUDIO_CLK_0		493
496 #define IMX_SC_R_AUDIO_CLK_1		494
497 #define IMX_SC_R_MCLK_OUT_0		495
498 #define IMX_SC_R_MCLK_OUT_1		496
499 #define IMX_SC_R_PMIC_0			497
500 #define IMX_SC_R_PMIC_1			498
501 #define IMX_SC_R_SECO			499
502 #define IMX_SC_R_CAAM_JR1		500
503 #define IMX_SC_R_CAAM_JR2		501
504 #define IMX_SC_R_CAAM_JR3		502
505 #define IMX_SC_R_SECO_MU_2		503
506 #define IMX_SC_R_SECO_MU_3		504
507 #define IMX_SC_R_SECO_MU_4		505
508 #define IMX_SC_R_HDMI_RX_PWM_0		506
509 #define IMX_SC_R_A35			507
510 #define IMX_SC_R_A35_0			508
511 #define IMX_SC_R_A35_1			509
512 #define IMX_SC_R_A35_2			510
513 #define IMX_SC_R_A35_3			511
514 #define IMX_SC_R_DSP			512
515 #define IMX_SC_R_DSP_RAM		513
516 #define IMX_SC_R_CAAM_JR1_OUT		514
517 #define IMX_SC_R_CAAM_JR2_OUT		515
518 #define IMX_SC_R_CAAM_JR3_OUT		516
519 #define IMX_SC_R_VPU_DEC_0		517
520 #define IMX_SC_R_VPU_ENC_0		518
521 #define IMX_SC_R_CAAM_JR0		519
522 #define IMX_SC_R_CAAM_JR0_OUT		520
523 #define IMX_SC_R_PMIC_2			521
524 #define IMX_SC_R_DBLOGIC		522
525 #define IMX_SC_R_HDMI_PLL_1		523
526 #define IMX_SC_R_BOARD_R0		524
527 #define IMX_SC_R_BOARD_R1		525
528 #define IMX_SC_R_BOARD_R2		526
529 #define IMX_SC_R_BOARD_R3		527
530 #define IMX_SC_R_BOARD_R4		528
531 #define IMX_SC_R_BOARD_R5		529
532 #define IMX_SC_R_BOARD_R6		530
533 #define IMX_SC_R_BOARD_R7		531
534 #define IMX_SC_R_MJPEG_DEC_MP		532
535 #define IMX_SC_R_MJPEG_ENC_MP		533
536 #define IMX_SC_R_VPU_TS_0		534
537 #define IMX_SC_R_VPU_MU_0		535
538 #define IMX_SC_R_VPU_MU_1		536
539 #define IMX_SC_R_VPU_MU_2		537
540 #define IMX_SC_R_VPU_MU_3		538
541 #define IMX_SC_R_VPU_ENC_1		539
542 #define IMX_SC_R_VPU			540
543 #define IMX_SC_R_DMA_5_CH0		541
544 #define IMX_SC_R_DMA_5_CH1		542
545 #define IMX_SC_R_DMA_5_CH2		543
546 #define IMX_SC_R_DMA_5_CH3		544
547 #define IMX_SC_R_ATTESTATION		545
548 #define IMX_SC_R_LAST			546
549 
550 #endif /* __DT_BINDINGS_RSCRC_IMX_H */
551