135254680SRajan Vaja /* SPDX-License-Identifier: GPL-2.0 */ 235254680SRajan Vaja /* 335254680SRajan Vaja * Copyright (C) 2019 Xilinx Inc. 435254680SRajan Vaja * 535254680SRajan Vaja */ 635254680SRajan Vaja 735254680SRajan Vaja #ifndef _DT_BINDINGS_CLK_VERSAL_H 835254680SRajan Vaja #define _DT_BINDINGS_CLK_VERSAL_H 935254680SRajan Vaja 1035254680SRajan Vaja #define PMC_PLL 1 1135254680SRajan Vaja #define APU_PLL 2 1235254680SRajan Vaja #define RPU_PLL 3 1335254680SRajan Vaja #define CPM_PLL 4 1435254680SRajan Vaja #define NOC_PLL 5 1535254680SRajan Vaja #define PLL_MAX 6 1635254680SRajan Vaja #define PMC_PRESRC 7 1735254680SRajan Vaja #define PMC_POSTCLK 8 1835254680SRajan Vaja #define PMC_PLL_OUT 9 1935254680SRajan Vaja #define PPLL 10 2035254680SRajan Vaja #define NOC_PRESRC 11 2135254680SRajan Vaja #define NOC_POSTCLK 12 2235254680SRajan Vaja #define NOC_PLL_OUT 13 2335254680SRajan Vaja #define NPLL 14 2435254680SRajan Vaja #define APU_PRESRC 15 2535254680SRajan Vaja #define APU_POSTCLK 16 2635254680SRajan Vaja #define APU_PLL_OUT 17 2735254680SRajan Vaja #define APLL 18 2835254680SRajan Vaja #define RPU_PRESRC 19 2935254680SRajan Vaja #define RPU_POSTCLK 20 3035254680SRajan Vaja #define RPU_PLL_OUT 21 3135254680SRajan Vaja #define RPLL 22 3235254680SRajan Vaja #define CPM_PRESRC 23 3335254680SRajan Vaja #define CPM_POSTCLK 24 3435254680SRajan Vaja #define CPM_PLL_OUT 25 3535254680SRajan Vaja #define CPLL 26 3635254680SRajan Vaja #define PPLL_TO_XPD 27 3735254680SRajan Vaja #define NPLL_TO_XPD 28 3835254680SRajan Vaja #define APLL_TO_XPD 29 3935254680SRajan Vaja #define RPLL_TO_XPD 30 4035254680SRajan Vaja #define EFUSE_REF 31 4135254680SRajan Vaja #define SYSMON_REF 32 4235254680SRajan Vaja #define IRO_SUSPEND_REF 33 4335254680SRajan Vaja #define USB_SUSPEND 34 4435254680SRajan Vaja #define SWITCH_TIMEOUT 35 4535254680SRajan Vaja #define RCLK_PMC 36 4635254680SRajan Vaja #define RCLK_LPD 37 4735254680SRajan Vaja #define WDT 38 4835254680SRajan Vaja #define TTC0 39 4935254680SRajan Vaja #define TTC1 40 5035254680SRajan Vaja #define TTC2 41 5135254680SRajan Vaja #define TTC3 42 5235254680SRajan Vaja #define GEM_TSU 43 5335254680SRajan Vaja #define GEM_TSU_LB 44 5435254680SRajan Vaja #define MUXED_IRO_DIV2 45 5535254680SRajan Vaja #define MUXED_IRO_DIV4 46 5635254680SRajan Vaja #define PSM_REF 47 5735254680SRajan Vaja #define GEM0_RX 48 5835254680SRajan Vaja #define GEM0_TX 49 5935254680SRajan Vaja #define GEM1_RX 50 6035254680SRajan Vaja #define GEM1_TX 51 6135254680SRajan Vaja #define CPM_CORE_REF 52 6235254680SRajan Vaja #define CPM_LSBUS_REF 53 6335254680SRajan Vaja #define CPM_DBG_REF 54 6435254680SRajan Vaja #define CPM_AUX0_REF 55 6535254680SRajan Vaja #define CPM_AUX1_REF 56 6635254680SRajan Vaja #define QSPI_REF 57 6735254680SRajan Vaja #define OSPI_REF 58 6835254680SRajan Vaja #define SDIO0_REF 59 6935254680SRajan Vaja #define SDIO1_REF 60 7035254680SRajan Vaja #define PMC_LSBUS_REF 61 7135254680SRajan Vaja #define I2C_REF 62 7235254680SRajan Vaja #define TEST_PATTERN_REF 63 7335254680SRajan Vaja #define DFT_OSC_REF 64 7435254680SRajan Vaja #define PMC_PL0_REF 65 7535254680SRajan Vaja #define PMC_PL1_REF 66 7635254680SRajan Vaja #define PMC_PL2_REF 67 7735254680SRajan Vaja #define PMC_PL3_REF 68 7835254680SRajan Vaja #define CFU_REF 69 7935254680SRajan Vaja #define SPARE_REF 70 8035254680SRajan Vaja #define NPI_REF 71 8135254680SRajan Vaja #define HSM0_REF 72 8235254680SRajan Vaja #define HSM1_REF 73 8335254680SRajan Vaja #define SD_DLL_REF 74 8435254680SRajan Vaja #define FPD_TOP_SWITCH 75 8535254680SRajan Vaja #define FPD_LSBUS 76 8635254680SRajan Vaja #define ACPU 77 8735254680SRajan Vaja #define DBG_TRACE 78 8835254680SRajan Vaja #define DBG_FPD 79 8935254680SRajan Vaja #define LPD_TOP_SWITCH 80 9035254680SRajan Vaja #define ADMA 81 9135254680SRajan Vaja #define LPD_LSBUS 82 9235254680SRajan Vaja #define CPU_R5 83 9335254680SRajan Vaja #define CPU_R5_CORE 84 9435254680SRajan Vaja #define CPU_R5_OCM 85 9535254680SRajan Vaja #define CPU_R5_OCM2 86 9635254680SRajan Vaja #define IOU_SWITCH 87 9735254680SRajan Vaja #define GEM0_REF 88 9835254680SRajan Vaja #define GEM1_REF 89 9935254680SRajan Vaja #define GEM_TSU_REF 90 10035254680SRajan Vaja #define USB0_BUS_REF 91 10135254680SRajan Vaja #define UART0_REF 92 10235254680SRajan Vaja #define UART1_REF 93 10335254680SRajan Vaja #define SPI0_REF 94 10435254680SRajan Vaja #define SPI1_REF 95 10535254680SRajan Vaja #define CAN0_REF 96 10635254680SRajan Vaja #define CAN1_REF 97 10735254680SRajan Vaja #define I2C0_REF 98 10835254680SRajan Vaja #define I2C1_REF 99 10935254680SRajan Vaja #define DBG_LPD 100 11035254680SRajan Vaja #define TIMESTAMP_REF 101 11135254680SRajan Vaja #define DBG_TSTMP 102 11235254680SRajan Vaja #define CPM_TOPSW_REF 103 11335254680SRajan Vaja #define USB3_DUAL_REF 104 11435254680SRajan Vaja #define OUTCLK_MAX 105 11535254680SRajan Vaja #define REF_CLK 106 11635254680SRajan Vaja #define PL_ALT_REF_CLK 107 11735254680SRajan Vaja #define MUXED_IRO 108 11835254680SRajan Vaja #define PL_EXT 109 11935254680SRajan Vaja #define PL_LB 110 12035254680SRajan Vaja #define MIO_50_OR_51 111 12135254680SRajan Vaja #define MIO_24_OR_25 112 12235254680SRajan Vaja 12335254680SRajan Vaja #endif 124