12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
21f2c5fd5SJingchang Lu /*
31f2c5fd5SJingchang Lu  * Copyright 2013 Freescale Semiconductor, Inc.
41f2c5fd5SJingchang Lu  */
51f2c5fd5SJingchang Lu 
61f2c5fd5SJingchang Lu #ifndef __DT_BINDINGS_CLOCK_VF610_H
71f2c5fd5SJingchang Lu #define __DT_BINDINGS_CLOCK_VF610_H
81f2c5fd5SJingchang Lu 
91f2c5fd5SJingchang Lu #define VF610_CLK_DUMMY			0
101f2c5fd5SJingchang Lu #define VF610_CLK_SIRC_128K		1
111f2c5fd5SJingchang Lu #define VF610_CLK_SIRC_32K		2
121f2c5fd5SJingchang Lu #define VF610_CLK_FIRC			3
131f2c5fd5SJingchang Lu #define VF610_CLK_SXOSC			4
141f2c5fd5SJingchang Lu #define VF610_CLK_FXOSC			5
151f2c5fd5SJingchang Lu #define VF610_CLK_FXOSC_HALF		6
161f2c5fd5SJingchang Lu #define VF610_CLK_SLOW_CLK_SEL		7
171f2c5fd5SJingchang Lu #define VF610_CLK_FASK_CLK_SEL		8
181f2c5fd5SJingchang Lu #define VF610_CLK_AUDIO_EXT		9
191f2c5fd5SJingchang Lu #define VF610_CLK_ENET_EXT		10
20c72c5532SStefan Agner #define VF610_CLK_PLL1_SYS		11
211f2c5fd5SJingchang Lu #define VF610_CLK_PLL1_PFD1		12
221f2c5fd5SJingchang Lu #define VF610_CLK_PLL1_PFD2		13
231f2c5fd5SJingchang Lu #define VF610_CLK_PLL1_PFD3		14
241f2c5fd5SJingchang Lu #define VF610_CLK_PLL1_PFD4		15
25c72c5532SStefan Agner #define VF610_CLK_PLL2_BUS		16
261f2c5fd5SJingchang Lu #define VF610_CLK_PLL2_PFD1		17
271f2c5fd5SJingchang Lu #define VF610_CLK_PLL2_PFD2		18
281f2c5fd5SJingchang Lu #define VF610_CLK_PLL2_PFD3		19
291f2c5fd5SJingchang Lu #define VF610_CLK_PLL2_PFD4		20
30c72c5532SStefan Agner #define VF610_CLK_PLL3_USB_OTG		21
311f2c5fd5SJingchang Lu #define VF610_CLK_PLL3_PFD1		22
321f2c5fd5SJingchang Lu #define VF610_CLK_PLL3_PFD2		23
331f2c5fd5SJingchang Lu #define VF610_CLK_PLL3_PFD3		24
341f2c5fd5SJingchang Lu #define VF610_CLK_PLL3_PFD4		25
35c72c5532SStefan Agner #define VF610_CLK_PLL4_AUDIO		26
36c72c5532SStefan Agner #define VF610_CLK_PLL5_ENET		27
37c72c5532SStefan Agner #define VF610_CLK_PLL6_VIDEO		28
381f2c5fd5SJingchang Lu #define VF610_CLK_PLL3_MAIN_DIV		29
391f2c5fd5SJingchang Lu #define VF610_CLK_PLL4_MAIN_DIV		30
401f2c5fd5SJingchang Lu #define VF610_CLK_PLL6_MAIN_DIV		31
411f2c5fd5SJingchang Lu #define VF610_CLK_PLL1_PFD_SEL		32
421f2c5fd5SJingchang Lu #define VF610_CLK_PLL2_PFD_SEL		33
431f2c5fd5SJingchang Lu #define VF610_CLK_SYS_SEL		34
441f2c5fd5SJingchang Lu #define VF610_CLK_DDR_SEL		35
451f2c5fd5SJingchang Lu #define VF610_CLK_SYS_BUS		36
461f2c5fd5SJingchang Lu #define VF610_CLK_PLATFORM_BUS		37
471f2c5fd5SJingchang Lu #define VF610_CLK_IPG_BUS		38
481f2c5fd5SJingchang Lu #define VF610_CLK_UART0			39
491f2c5fd5SJingchang Lu #define VF610_CLK_UART1			40
501f2c5fd5SJingchang Lu #define VF610_CLK_UART2			41
511f2c5fd5SJingchang Lu #define VF610_CLK_UART3			42
521f2c5fd5SJingchang Lu #define VF610_CLK_UART4			43
531f2c5fd5SJingchang Lu #define VF610_CLK_UART5			44
541f2c5fd5SJingchang Lu #define VF610_CLK_PIT			45
551f2c5fd5SJingchang Lu #define VF610_CLK_I2C0			46
561f2c5fd5SJingchang Lu #define VF610_CLK_I2C1			47
571f2c5fd5SJingchang Lu #define VF610_CLK_I2C2			48
581f2c5fd5SJingchang Lu #define VF610_CLK_I2C3			49
591f2c5fd5SJingchang Lu #define VF610_CLK_FTM0_EXT_SEL		50
601f2c5fd5SJingchang Lu #define VF610_CLK_FTM0_FIX_SEL		51
611f2c5fd5SJingchang Lu #define VF610_CLK_FTM0_EXT_FIX_EN	52
621f2c5fd5SJingchang Lu #define VF610_CLK_FTM1_EXT_SEL		53
631f2c5fd5SJingchang Lu #define VF610_CLK_FTM1_FIX_SEL		54
641f2c5fd5SJingchang Lu #define VF610_CLK_FTM1_EXT_FIX_EN	55
651f2c5fd5SJingchang Lu #define VF610_CLK_FTM2_EXT_SEL		56
661f2c5fd5SJingchang Lu #define VF610_CLK_FTM2_FIX_SEL		57
671f2c5fd5SJingchang Lu #define VF610_CLK_FTM2_EXT_FIX_EN	58
681f2c5fd5SJingchang Lu #define VF610_CLK_FTM3_EXT_SEL		59
691f2c5fd5SJingchang Lu #define VF610_CLK_FTM3_FIX_SEL		60
701f2c5fd5SJingchang Lu #define VF610_CLK_FTM3_EXT_FIX_EN	61
711f2c5fd5SJingchang Lu #define VF610_CLK_FTM0			62
721f2c5fd5SJingchang Lu #define VF610_CLK_FTM1			63
731f2c5fd5SJingchang Lu #define VF610_CLK_FTM2			64
741f2c5fd5SJingchang Lu #define VF610_CLK_FTM3			65
751f2c5fd5SJingchang Lu #define VF610_CLK_ENET_50M		66
761f2c5fd5SJingchang Lu #define VF610_CLK_ENET_25M		67
771f2c5fd5SJingchang Lu #define VF610_CLK_ENET_SEL		68
781f2c5fd5SJingchang Lu #define VF610_CLK_ENET			69
791f2c5fd5SJingchang Lu #define VF610_CLK_ENET_TS_SEL		70
801f2c5fd5SJingchang Lu #define VF610_CLK_ENET_TS		71
811f2c5fd5SJingchang Lu #define VF610_CLK_DSPI0			72
821f2c5fd5SJingchang Lu #define VF610_CLK_DSPI1			73
831f2c5fd5SJingchang Lu #define VF610_CLK_DSPI2			74
841f2c5fd5SJingchang Lu #define VF610_CLK_DSPI3			75
851f2c5fd5SJingchang Lu #define VF610_CLK_WDT			76
861f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC0_SEL		77
871f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC0_EN		78
881f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC0_DIV		79
891f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC0		80
901f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC1_SEL		81
911f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC1_EN		82
921f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC1_DIV		83
931f2c5fd5SJingchang Lu #define VF610_CLK_ESDHC1		84
941f2c5fd5SJingchang Lu #define VF610_CLK_DCU0_SEL		85
951f2c5fd5SJingchang Lu #define VF610_CLK_DCU0_EN		86
961f2c5fd5SJingchang Lu #define VF610_CLK_DCU0_DIV		87
971f2c5fd5SJingchang Lu #define VF610_CLK_DCU0			88
981f2c5fd5SJingchang Lu #define VF610_CLK_DCU1_SEL		89
991f2c5fd5SJingchang Lu #define VF610_CLK_DCU1_EN		90
1001f2c5fd5SJingchang Lu #define VF610_CLK_DCU1_DIV		91
1011f2c5fd5SJingchang Lu #define VF610_CLK_DCU1			92
1021f2c5fd5SJingchang Lu #define VF610_CLK_ESAI_SEL		93
1031f2c5fd5SJingchang Lu #define VF610_CLK_ESAI_EN		94
1041f2c5fd5SJingchang Lu #define VF610_CLK_ESAI_DIV		95
1051f2c5fd5SJingchang Lu #define VF610_CLK_ESAI			96
1061f2c5fd5SJingchang Lu #define VF610_CLK_SAI0_SEL		97
1071f2c5fd5SJingchang Lu #define VF610_CLK_SAI0_EN		98
1081f2c5fd5SJingchang Lu #define VF610_CLK_SAI0_DIV		99
1091f2c5fd5SJingchang Lu #define VF610_CLK_SAI0			100
1101f2c5fd5SJingchang Lu #define VF610_CLK_SAI1_SEL		101
1111f2c5fd5SJingchang Lu #define VF610_CLK_SAI1_EN		102
1121f2c5fd5SJingchang Lu #define VF610_CLK_SAI1_DIV		103
1131f2c5fd5SJingchang Lu #define VF610_CLK_SAI1			104
1141f2c5fd5SJingchang Lu #define VF610_CLK_SAI2_SEL		105
1151f2c5fd5SJingchang Lu #define VF610_CLK_SAI2_EN		106
1161f2c5fd5SJingchang Lu #define VF610_CLK_SAI2_DIV		107
1171f2c5fd5SJingchang Lu #define VF610_CLK_SAI2			108
1181f2c5fd5SJingchang Lu #define VF610_CLK_SAI3_SEL		109
1191f2c5fd5SJingchang Lu #define VF610_CLK_SAI3_EN		110
1201f2c5fd5SJingchang Lu #define VF610_CLK_SAI3_DIV		111
1211f2c5fd5SJingchang Lu #define VF610_CLK_SAI3			112
1221f2c5fd5SJingchang Lu #define VF610_CLK_USBC0			113
1231f2c5fd5SJingchang Lu #define VF610_CLK_USBC1			114
1241f2c5fd5SJingchang Lu #define VF610_CLK_QSPI0_SEL		115
1251f2c5fd5SJingchang Lu #define VF610_CLK_QSPI0_EN		116
1261f2c5fd5SJingchang Lu #define VF610_CLK_QSPI0_X4_DIV		117
1271f2c5fd5SJingchang Lu #define VF610_CLK_QSPI0_X2_DIV		118
1281f2c5fd5SJingchang Lu #define VF610_CLK_QSPI0_X1_DIV		119
1291f2c5fd5SJingchang Lu #define VF610_CLK_QSPI1_SEL		120
1301f2c5fd5SJingchang Lu #define VF610_CLK_QSPI1_EN		121
1311f2c5fd5SJingchang Lu #define VF610_CLK_QSPI1_X4_DIV		122
1321f2c5fd5SJingchang Lu #define VF610_CLK_QSPI1_X2_DIV		123
1331f2c5fd5SJingchang Lu #define VF610_CLK_QSPI1_X1_DIV		124
1341f2c5fd5SJingchang Lu #define VF610_CLK_QSPI0			125
1351f2c5fd5SJingchang Lu #define VF610_CLK_QSPI1			126
1361f2c5fd5SJingchang Lu #define VF610_CLK_NFC_SEL		127
1371f2c5fd5SJingchang Lu #define VF610_CLK_NFC_EN		128
1381f2c5fd5SJingchang Lu #define VF610_CLK_NFC_PRE_DIV		129
1391f2c5fd5SJingchang Lu #define VF610_CLK_NFC_FRAC_DIV		130
1401f2c5fd5SJingchang Lu #define VF610_CLK_NFC_INV		131
1411f2c5fd5SJingchang Lu #define VF610_CLK_NFC			132
1421f2c5fd5SJingchang Lu #define VF610_CLK_VADC_SEL		133
1431f2c5fd5SJingchang Lu #define VF610_CLK_VADC_EN		134
1441f2c5fd5SJingchang Lu #define VF610_CLK_VADC_DIV		135
1451f2c5fd5SJingchang Lu #define VF610_CLK_VADC_DIV_HALF		136
1461f2c5fd5SJingchang Lu #define VF610_CLK_VADC			137
1471f2c5fd5SJingchang Lu #define VF610_CLK_ADC0			138
1481f2c5fd5SJingchang Lu #define VF610_CLK_ADC1			139
1491f2c5fd5SJingchang Lu #define VF610_CLK_DAC0			140
1501f2c5fd5SJingchang Lu #define VF610_CLK_DAC1			141
1511f2c5fd5SJingchang Lu #define VF610_CLK_FLEXCAN0		142
1521f2c5fd5SJingchang Lu #define VF610_CLK_FLEXCAN1		143
1531f2c5fd5SJingchang Lu #define VF610_CLK_ASRC			144
1541f2c5fd5SJingchang Lu #define VF610_CLK_GPU_SEL		145
1551f2c5fd5SJingchang Lu #define VF610_CLK_GPU_EN		146
1561f2c5fd5SJingchang Lu #define VF610_CLK_GPU2D			147
1574f71612eSShawn Guo #define VF610_CLK_ENET0			148
1584f71612eSShawn Guo #define VF610_CLK_ENET1			149
159daaff6e9SJingchang Lu #define VF610_CLK_DMAMUX0		150
160daaff6e9SJingchang Lu #define VF610_CLK_DMAMUX1		151
161daaff6e9SJingchang Lu #define VF610_CLK_DMAMUX2		152
162daaff6e9SJingchang Lu #define VF610_CLK_DMAMUX3		153
1634349c429SStefan Agner #define VF610_CLK_FLEXCAN0_EN		154
1644349c429SStefan Agner #define VF610_CLK_FLEXCAN1_EN		155
165c72c5532SStefan Agner #define VF610_CLK_PLL7_USB_HOST		156
16621231f81SStefan Agner #define VF610_CLK_USBPHY0		157
16721231f81SStefan Agner #define VF610_CLK_USBPHY1		158
168c72c5532SStefan Agner #define VF610_CLK_LVDS1_IN		159
169c72c5532SStefan Agner #define VF610_CLK_ANACLK1		160
170c72c5532SStefan Agner #define VF610_CLK_PLL1_BYPASS_SRC	161
171c72c5532SStefan Agner #define VF610_CLK_PLL2_BYPASS_SRC	162
172c72c5532SStefan Agner #define VF610_CLK_PLL3_BYPASS_SRC	163
173c72c5532SStefan Agner #define VF610_CLK_PLL4_BYPASS_SRC	164
174c72c5532SStefan Agner #define VF610_CLK_PLL5_BYPASS_SRC	165
175c72c5532SStefan Agner #define VF610_CLK_PLL6_BYPASS_SRC	166
176c72c5532SStefan Agner #define VF610_CLK_PLL7_BYPASS_SRC	167
177c72c5532SStefan Agner #define VF610_CLK_PLL1			168
178c72c5532SStefan Agner #define VF610_CLK_PLL2			169
179c72c5532SStefan Agner #define VF610_CLK_PLL3			170
180c72c5532SStefan Agner #define VF610_CLK_PLL4			171
181c72c5532SStefan Agner #define VF610_CLK_PLL5			172
182c72c5532SStefan Agner #define VF610_CLK_PLL6			173
183c72c5532SStefan Agner #define VF610_CLK_PLL7			174
184c72c5532SStefan Agner #define VF610_PLL1_BYPASS		175
185c72c5532SStefan Agner #define VF610_PLL2_BYPASS		176
186c72c5532SStefan Agner #define VF610_PLL3_BYPASS		177
187c72c5532SStefan Agner #define VF610_PLL4_BYPASS		178
188c72c5532SStefan Agner #define VF610_PLL5_BYPASS		179
189c72c5532SStefan Agner #define VF610_PLL6_BYPASS		180
190c72c5532SStefan Agner #define VF610_PLL7_BYPASS		181
191c2053895SSanchayan Maity #define VF610_CLK_SNVS			182
192d930d568SStefan Agner #define VF610_CLK_DAP			183
1930753f56eSSanchayan Maity #define VF610_CLK_OCOTP			184
1940da15d36SStefan Agner #define VF610_CLK_DDRMC			185
195349efbeeSStefan Agner #define VF610_CLK_WKPU			186
196afd7350aSStefan Agner #define VF610_CLK_TCON0			187
197afd7350aSStefan Agner #define VF610_CLK_TCON1			188
198018e4308SAndrey Smirnov #define VF610_CLK_CAAM			189
1990b805610SKrzysztof Kozlowski #define VF610_CLK_CRC			190
2000b805610SKrzysztof Kozlowski #define VF610_CLK_END			191
2011f2c5fd5SJingchang Lu 
2021f2c5fd5SJingchang Lu #endif /* __DT_BINDINGS_CLOCK_VF610_H */
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