19513109dSHiroshi Doyu /* 29513109dSHiroshi Doyu * This header provides constants for binding nvidia,tegra30-car. 39513109dSHiroshi Doyu * 49513109dSHiroshi Doyu * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 59513109dSHiroshi Doyu * registers. These IDs often match those in the CAR's RST_DEVICES registers, 69513109dSHiroshi Doyu * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 79513109dSHiroshi Doyu * this case, those clocks are assigned IDs above 160 in order to highlight 89513109dSHiroshi Doyu * this issue. Implementations that interpret these clock IDs as bit values 99513109dSHiroshi Doyu * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 109513109dSHiroshi Doyu * explicitly handle these special cases. 119513109dSHiroshi Doyu * 129513109dSHiroshi Doyu * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 139513109dSHiroshi Doyu * above. 149513109dSHiroshi Doyu */ 159513109dSHiroshi Doyu 169513109dSHiroshi Doyu #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 179513109dSHiroshi Doyu #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 189513109dSHiroshi Doyu 199513109dSHiroshi Doyu #define TEGRA30_CLK_CPU 0 209513109dSHiroshi Doyu /* 1 */ 219513109dSHiroshi Doyu /* 2 */ 229513109dSHiroshi Doyu /* 3 */ 239513109dSHiroshi Doyu #define TEGRA30_CLK_RTC 4 249513109dSHiroshi Doyu #define TEGRA30_CLK_TIMER 5 259513109dSHiroshi Doyu #define TEGRA30_CLK_UARTA 6 269513109dSHiroshi Doyu /* 7 (register bit affects uartb and vfir) */ 279513109dSHiroshi Doyu #define TEGRA30_CLK_GPIO 8 289513109dSHiroshi Doyu #define TEGRA30_CLK_SDMMC2 9 299513109dSHiroshi Doyu /* 10 (register bit affects spdif_in and spdif_out) */ 309513109dSHiroshi Doyu #define TEGRA30_CLK_I2S1 11 319513109dSHiroshi Doyu #define TEGRA30_CLK_I2C1 12 329513109dSHiroshi Doyu #define TEGRA30_CLK_NDFLASH 13 339513109dSHiroshi Doyu #define TEGRA30_CLK_SDMMC1 14 349513109dSHiroshi Doyu #define TEGRA30_CLK_SDMMC4 15 359513109dSHiroshi Doyu /* 16 */ 369513109dSHiroshi Doyu #define TEGRA30_CLK_PWM 17 379513109dSHiroshi Doyu #define TEGRA30_CLK_I2S2 18 389513109dSHiroshi Doyu #define TEGRA30_CLK_EPP 19 399513109dSHiroshi Doyu /* 20 (register bit affects vi and vi_sensor) */ 409513109dSHiroshi Doyu #define TEGRA30_CLK_GR2D 21 419513109dSHiroshi Doyu #define TEGRA30_CLK_USBD 22 429513109dSHiroshi Doyu #define TEGRA30_CLK_ISP 23 439513109dSHiroshi Doyu #define TEGRA30_CLK_GR3D 24 449513109dSHiroshi Doyu /* 25 */ 459513109dSHiroshi Doyu #define TEGRA30_CLK_DISP2 26 469513109dSHiroshi Doyu #define TEGRA30_CLK_DISP1 27 479513109dSHiroshi Doyu #define TEGRA30_CLK_HOST1X 28 489513109dSHiroshi Doyu #define TEGRA30_CLK_VCP 29 499513109dSHiroshi Doyu #define TEGRA30_CLK_I2S0 30 509513109dSHiroshi Doyu #define TEGRA30_CLK_COP_CACHE 31 519513109dSHiroshi Doyu 529513109dSHiroshi Doyu #define TEGRA30_CLK_MC 32 539513109dSHiroshi Doyu #define TEGRA30_CLK_AHBDMA 33 549513109dSHiroshi Doyu #define TEGRA30_CLK_APBDMA 34 559513109dSHiroshi Doyu /* 35 */ 569513109dSHiroshi Doyu #define TEGRA30_CLK_KBC 36 579513109dSHiroshi Doyu #define TEGRA30_CLK_STATMON 37 589513109dSHiroshi Doyu #define TEGRA30_CLK_PMC 38 599513109dSHiroshi Doyu /* 39 (register bit affects fuse and fuse_burn) */ 609513109dSHiroshi Doyu #define TEGRA30_CLK_KFUSE 40 619513109dSHiroshi Doyu #define TEGRA30_CLK_SBC1 41 629513109dSHiroshi Doyu #define TEGRA30_CLK_NOR 42 639513109dSHiroshi Doyu /* 43 */ 649513109dSHiroshi Doyu #define TEGRA30_CLK_SBC2 44 659513109dSHiroshi Doyu /* 45 */ 669513109dSHiroshi Doyu #define TEGRA30_CLK_SBC3 46 679513109dSHiroshi Doyu #define TEGRA30_CLK_I2C5 47 689513109dSHiroshi Doyu #define TEGRA30_CLK_DSIA 48 699513109dSHiroshi Doyu /* 49 (register bit affects cve and tvo) */ 709513109dSHiroshi Doyu #define TEGRA30_CLK_MIPI 50 719513109dSHiroshi Doyu #define TEGRA30_CLK_HDMI 51 729513109dSHiroshi Doyu #define TEGRA30_CLK_CSI 52 739513109dSHiroshi Doyu #define TEGRA30_CLK_TVDAC 53 749513109dSHiroshi Doyu #define TEGRA30_CLK_I2C2 54 759513109dSHiroshi Doyu #define TEGRA30_CLK_UARTC 55 769513109dSHiroshi Doyu /* 56 */ 779513109dSHiroshi Doyu #define TEGRA30_CLK_EMC 57 789513109dSHiroshi Doyu #define TEGRA30_CLK_USB2 58 799513109dSHiroshi Doyu #define TEGRA30_CLK_USB3 59 809513109dSHiroshi Doyu #define TEGRA30_CLK_MPE 60 819513109dSHiroshi Doyu #define TEGRA30_CLK_VDE 61 829513109dSHiroshi Doyu #define TEGRA30_CLK_BSEA 62 839513109dSHiroshi Doyu #define TEGRA30_CLK_BSEV 63 849513109dSHiroshi Doyu 859513109dSHiroshi Doyu #define TEGRA30_CLK_SPEEDO 64 869513109dSHiroshi Doyu #define TEGRA30_CLK_UARTD 65 879513109dSHiroshi Doyu #define TEGRA30_CLK_UARTE 66 889513109dSHiroshi Doyu #define TEGRA30_CLK_I2C3 67 899513109dSHiroshi Doyu #define TEGRA30_CLK_SBC4 68 909513109dSHiroshi Doyu #define TEGRA30_CLK_SDMMC3 69 919513109dSHiroshi Doyu #define TEGRA30_CLK_PCIE 70 929513109dSHiroshi Doyu #define TEGRA30_CLK_OWR 71 939513109dSHiroshi Doyu #define TEGRA30_CLK_AFI 72 949513109dSHiroshi Doyu #define TEGRA30_CLK_CSITE 73 959513109dSHiroshi Doyu #define TEGRA30_CLK_PCIEX 74 969513109dSHiroshi Doyu #define TEGRA30_CLK_AVPUCQ 75 979513109dSHiroshi Doyu #define TEGRA30_CLK_LA 76 989513109dSHiroshi Doyu /* 77 */ 999513109dSHiroshi Doyu /* 78 */ 1009513109dSHiroshi Doyu #define TEGRA30_CLK_DTV 79 1019513109dSHiroshi Doyu #define TEGRA30_CLK_NDSPEED 80 1029513109dSHiroshi Doyu #define TEGRA30_CLK_I2CSLOW 81 1039513109dSHiroshi Doyu #define TEGRA30_CLK_DSIB 82 1049513109dSHiroshi Doyu /* 83 */ 1059513109dSHiroshi Doyu #define TEGRA30_CLK_IRAMA 84 1069513109dSHiroshi Doyu #define TEGRA30_CLK_IRAMB 85 1079513109dSHiroshi Doyu #define TEGRA30_CLK_IRAMC 86 1089513109dSHiroshi Doyu #define TEGRA30_CLK_IRAMD 87 1099513109dSHiroshi Doyu #define TEGRA30_CLK_CRAM2 88 1109513109dSHiroshi Doyu /* 89 */ 1119513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 1129513109dSHiroshi Doyu /* 91 */ 1139513109dSHiroshi Doyu #define TEGRA30_CLK_CSUS 92 1149513109dSHiroshi Doyu #define TEGRA30_CLK_CDEV2 93 1159513109dSHiroshi Doyu #define TEGRA30_CLK_CDEV1 94 1169513109dSHiroshi Doyu /* 95 */ 1179513109dSHiroshi Doyu 1189513109dSHiroshi Doyu #define TEGRA30_CLK_CPU_G 96 1199513109dSHiroshi Doyu #define TEGRA30_CLK_CPU_LP 97 1209513109dSHiroshi Doyu #define TEGRA30_CLK_GR3D2 98 1219513109dSHiroshi Doyu #define TEGRA30_CLK_MSELECT 99 1229513109dSHiroshi Doyu #define TEGRA30_CLK_TSENSOR 100 1239513109dSHiroshi Doyu #define TEGRA30_CLK_I2S3 101 1249513109dSHiroshi Doyu #define TEGRA30_CLK_I2S4 102 1259513109dSHiroshi Doyu #define TEGRA30_CLK_I2C4 103 1269513109dSHiroshi Doyu #define TEGRA30_CLK_SBC5 104 1279513109dSHiroshi Doyu #define TEGRA30_CLK_SBC6 105 1289513109dSHiroshi Doyu #define TEGRA30_CLK_D_AUDIO 106 1299513109dSHiroshi Doyu #define TEGRA30_CLK_APBIF 107 1309513109dSHiroshi Doyu #define TEGRA30_CLK_DAM0 108 1319513109dSHiroshi Doyu #define TEGRA30_CLK_DAM1 109 1329513109dSHiroshi Doyu #define TEGRA30_CLK_DAM2 110 1339513109dSHiroshi Doyu #define TEGRA30_CLK_HDA2CODEC_2X 111 1349513109dSHiroshi Doyu #define TEGRA30_CLK_ATOMICS 112 1359513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO0_2X 113 1369513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO1_2X 114 1379513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO2_2X 115 1389513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO3_2X 116 1399513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO4_2X 117 1409513109dSHiroshi Doyu #define TEGRA30_CLK_SPDIF_2X 118 1419513109dSHiroshi Doyu #define TEGRA30_CLK_ACTMON 119 1429513109dSHiroshi Doyu #define TEGRA30_CLK_EXTERN1 120 1439513109dSHiroshi Doyu #define TEGRA30_CLK_EXTERN2 121 1449513109dSHiroshi Doyu #define TEGRA30_CLK_EXTERN3 122 1459513109dSHiroshi Doyu #define TEGRA30_CLK_SATA_OOB 123 1469513109dSHiroshi Doyu #define TEGRA30_CLK_SATA 124 1479513109dSHiroshi Doyu #define TEGRA30_CLK_HDA 125 1489513109dSHiroshi Doyu /* 126 */ 1499513109dSHiroshi Doyu #define TEGRA30_CLK_SE 127 1509513109dSHiroshi Doyu 1519513109dSHiroshi Doyu #define TEGRA30_CLK_HDA2HDMI 128 1529513109dSHiroshi Doyu #define TEGRA30_CLK_SATA_COLD 129 1539513109dSHiroshi Doyu /* 130 */ 1549513109dSHiroshi Doyu /* 131 */ 1559513109dSHiroshi Doyu /* 132 */ 1569513109dSHiroshi Doyu /* 133 */ 1579513109dSHiroshi Doyu /* 134 */ 1589513109dSHiroshi Doyu /* 135 */ 1599513109dSHiroshi Doyu /* 136 */ 1609513109dSHiroshi Doyu /* 137 */ 1619513109dSHiroshi Doyu /* 138 */ 1629513109dSHiroshi Doyu /* 139 */ 1639513109dSHiroshi Doyu /* 140 */ 1649513109dSHiroshi Doyu /* 141 */ 1659513109dSHiroshi Doyu /* 142 */ 1669513109dSHiroshi Doyu /* 143 */ 1679513109dSHiroshi Doyu /* 144 */ 1689513109dSHiroshi Doyu /* 145 */ 1699513109dSHiroshi Doyu /* 146 */ 1709513109dSHiroshi Doyu /* 147 */ 1719513109dSHiroshi Doyu /* 148 */ 1729513109dSHiroshi Doyu /* 149 */ 1739513109dSHiroshi Doyu /* 150 */ 1749513109dSHiroshi Doyu /* 151 */ 1759513109dSHiroshi Doyu /* 152 */ 1769513109dSHiroshi Doyu /* 153 */ 1779513109dSHiroshi Doyu /* 154 */ 1789513109dSHiroshi Doyu /* 155 */ 1799513109dSHiroshi Doyu /* 156 */ 1809513109dSHiroshi Doyu /* 157 */ 1819513109dSHiroshi Doyu /* 158 */ 1829513109dSHiroshi Doyu /* 159 */ 1839513109dSHiroshi Doyu 1849513109dSHiroshi Doyu #define TEGRA30_CLK_UARTB 160 1859513109dSHiroshi Doyu #define TEGRA30_CLK_VFIR 161 1869513109dSHiroshi Doyu #define TEGRA30_CLK_SPDIF_IN 162 1879513109dSHiroshi Doyu #define TEGRA30_CLK_SPDIF_OUT 163 1889513109dSHiroshi Doyu #define TEGRA30_CLK_VI 164 1899513109dSHiroshi Doyu #define TEGRA30_CLK_VI_SENSOR 165 1909513109dSHiroshi Doyu #define TEGRA30_CLK_FUSE 166 1919513109dSHiroshi Doyu #define TEGRA30_CLK_FUSE_BURN 167 1929513109dSHiroshi Doyu #define TEGRA30_CLK_CVE 168 1939513109dSHiroshi Doyu #define TEGRA30_CLK_TVO 169 1949513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_32K 170 1959513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_M 171 1969513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_M_DIV2 172 1979513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_M_DIV4 173 1989513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_REF 174 1999513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_C 175 2009513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_C_OUT1 176 2019513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_M 177 2029513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_M_OUT1 178 2039513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_P 179 2049513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_P_OUT1 180 2059513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_P_OUT2 181 2069513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_P_OUT3 182 2079513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_P_OUT4 183 2089513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_A 184 2099513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_A_OUT0 185 2109513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_D 186 2119513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_D_OUT0 187 2129513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_D2 188 2139513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_D2_OUT0 189 2149513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_U 190 2159513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_X 191 2169513109dSHiroshi Doyu 2179513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_X_OUT0 192 2189513109dSHiroshi Doyu #define TEGRA30_CLK_PLL_E 193 2199513109dSHiroshi Doyu #define TEGRA30_CLK_SPDIF_IN_SYNC 194 2209513109dSHiroshi Doyu #define TEGRA30_CLK_I2S0_SYNC 195 2219513109dSHiroshi Doyu #define TEGRA30_CLK_I2S1_SYNC 196 2229513109dSHiroshi Doyu #define TEGRA30_CLK_I2S2_SYNC 197 2239513109dSHiroshi Doyu #define TEGRA30_CLK_I2S3_SYNC 198 2249513109dSHiroshi Doyu #define TEGRA30_CLK_I2S4_SYNC 199 2259513109dSHiroshi Doyu #define TEGRA30_CLK_VIMCLK_SYNC 200 2269513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO0 201 2279513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO1 202 2289513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO2 203 2299513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO3 204 2309513109dSHiroshi Doyu #define TEGRA30_CLK_AUDIO4 205 2319513109dSHiroshi Doyu #define TEGRA30_CLK_SPDIF 206 2329513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 2339513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 2349513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 2359513109dSHiroshi Doyu #define TEGRA30_CLK_SCLK 210 2369513109dSHiroshi Doyu #define TEGRA30_CLK_BLINK 211 2379513109dSHiroshi Doyu #define TEGRA30_CLK_CCLK_G 212 2389513109dSHiroshi Doyu #define TEGRA30_CLK_CCLK_LP 213 2399513109dSHiroshi Doyu #define TEGRA30_CLK_TWD 214 2409513109dSHiroshi Doyu #define TEGRA30_CLK_CML0 215 2419513109dSHiroshi Doyu #define TEGRA30_CLK_CML1 216 2429513109dSHiroshi Doyu #define TEGRA30_CLK_HCLK 217 2439513109dSHiroshi Doyu #define TEGRA30_CLK_PCLK 218 2449513109dSHiroshi Doyu /* 219 */ 2459513109dSHiroshi Doyu /* 220 */ 2469513109dSHiroshi Doyu /* 221 */ 2479513109dSHiroshi Doyu /* 222 */ 2489513109dSHiroshi Doyu /* 223 */ 2499513109dSHiroshi Doyu 2509513109dSHiroshi Doyu /* 288 */ 2519513109dSHiroshi Doyu /* 289 */ 2529513109dSHiroshi Doyu /* 290 */ 2539513109dSHiroshi Doyu /* 291 */ 2549513109dSHiroshi Doyu /* 292 */ 2559513109dSHiroshi Doyu /* 293 */ 2569513109dSHiroshi Doyu /* 294 */ 2579513109dSHiroshi Doyu /* 295 */ 2589513109dSHiroshi Doyu /* 296 */ 2599513109dSHiroshi Doyu /* 297 */ 2609513109dSHiroshi Doyu /* 298 */ 2619513109dSHiroshi Doyu /* 299 */ 2629513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_OUT_1_MUX 300 2639513109dSHiroshi Doyu #define TEGRA30_CLK_CLK_MAX 301 2649513109dSHiroshi Doyu 2659513109dSHiroshi Doyu #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 266