1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
3 
4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
6 
7 /**
8  * @file
9  * @defgroup bpmp_clock_ids Clock ID's
10  * @{
11  */
12 /** @brief output of gate CLK_ENB_FUSE */
13 #define TEGRA234_CLK_FUSE			40U
14 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
15 #define TEGRA234_CLK_SDMMC4			123U
16 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
17 #define TEGRA234_CLK_UARTA			155U
18 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
19 #define TEGRA234_CLK_SDMMC_LEGACY_TM		219U
20 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
21 #define TEGRA234_CLK_PLLC4			237U
22 /** @brief 32K input clock provided by PMIC */
23 #define TEGRA234_CLK_CLK_32K			289U
24 
25 #endif
26