1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
3 
4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
6 
7 /**
8  * @file
9  * @defgroup bpmp_clock_ids Clock ID's
10  * @{
11  */
12 /**
13  * @brief controls the EMC clock frequency.
14  * @details Doing a clk_set_rate on this clock will select the
15  * appropriate clock source, program the source rate and execute a
16  * specific sequence to switch to the new clock source for both memory
17  * controllers. This can be used to control the balance between memory
18  * throughput and memory controller power.
19  */
20 #define TEGRA234_CLK_EMC			31U
21 /** @brief output of gate CLK_ENB_FUSE */
22 #define TEGRA234_CLK_FUSE			40U
23 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
24 #define TEGRA234_CLK_SDMMC4			123U
25 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
26 #define TEGRA234_CLK_UARTA			155U
27 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
28 #define TEGRA234_CLK_SDMMC_LEGACY_TM		219U
29 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
30 #define TEGRA234_CLK_PLLC4			237U
31 /** @brief 32K input clock provided by PMIC */
32 #define TEGRA234_CLK_CLK_32K			289U
33 
34 #endif
35