163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 263944891SThierry Reding /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 7*fc5e0e37SMikko Perttunen /** 8*fc5e0e37SMikko Perttunen * @file 9*fc5e0e37SMikko Perttunen * @defgroup bpmp_clock_ids Clock ID's 10*fc5e0e37SMikko Perttunen * @{ 11*fc5e0e37SMikko Perttunen */ 1263944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 13*fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE 40U 1463944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 15*fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4 123U 1663944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 17*fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA 155U 18*fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 19*fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 20*fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 21*fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4 237U 22*fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */ 23*fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K 289U 2463944891SThierry Reding 2563944891SThierry Reding #endif 26