163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 263944891SThierry Reding /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 7fc5e0e37SMikko Perttunen /** 8fc5e0e37SMikko Perttunen * @file 9fc5e0e37SMikko Perttunen * @defgroup bpmp_clock_ids Clock ID's 10fc5e0e37SMikko Perttunen * @{ 11fc5e0e37SMikko Perttunen */ 12*c3859c14SThierry Reding /** 13*c3859c14SThierry Reding * @brief controls the EMC clock frequency. 14*c3859c14SThierry Reding * @details Doing a clk_set_rate on this clock will select the 15*c3859c14SThierry Reding * appropriate clock source, program the source rate and execute a 16*c3859c14SThierry Reding * specific sequence to switch to the new clock source for both memory 17*c3859c14SThierry Reding * controllers. This can be used to control the balance between memory 18*c3859c14SThierry Reding * throughput and memory controller power. 19*c3859c14SThierry Reding */ 20*c3859c14SThierry Reding #define TEGRA234_CLK_EMC 31U 2163944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 22fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE 40U 2363944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 24fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4 123U 2563944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 26fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA 155U 27fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 28fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 29fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 30fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4 237U 31fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */ 32fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K 289U 3363944891SThierry Reding 3463944891SThierry Reding #endif 35